參數(shù)資料
型號(hào): PMS430E325AFZ
廠商: Texas Instruments, Inc.
英文描述: MIXED SIGNAL MICROCONTROLLER
中文描述: 混合信號(hào)微控制器
文件頁(yè)數(shù): 5/33頁(yè)
文件大小: 437K
代理商: PMS430E325AFZ
MSP430C32x, MSP430P325A
MIXED SIGNAL MICROCONTROLLER
SLAS219B – MARCH 1999 – REVISED MARCH 2000
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Table 2. Address Mode Descriptions
ADDRESS MODE
s
d
SYNTAX
EXAMPLE
OPERATION
Register
MOV Rs, Rd
MOV R10, R11
R10
R11
M(2 + R5)
M(6 + R6)
M(EDE)
M(TONI)
M(MEM)
M(TCDAT)
M(R10)
M(Tab + R6)
M(R10)
R11, R10 + 2
R10
#45
M(TONI)
Indexed
MOV X(Rn), Y(Rm)
MOV 2(R5), 5(R6)
Symbolic (PC relative)
MOV EDE, TONI
Absolute
MOV &MEM, &TCDAT
Indirect
MOV @Rn, Y(Rm)
MOV @R10, Tab(R6)
Indirect autoincrement
MOV @Rn+, RM
MOV @R10+, R11
Immediate
MOV #X, TONI
MOV #45, TONI
NOTE: s = source d = destination
Computed branches (BR) and subroutine calls (CALL) instructions use the same addressing modes as the other
instructions. These addressing modes provide indirectaddressing, ideally suited for computed branches and
calls. The full use of this programming capability permits a program structure different from conventional 8- and
16-bit controllers. For example, numerous routines can easily be designed to deal with pointers and stacks
instead of using flag type programs for flow control.
operation modes and interrupts
The MSP430 operating modes support various advanced requirements for ultra low power and ultra low energy
consumption. This is achieved by the intelligent management of the operations during the different module
operation modes and CPU states. The requirements are fully supported during interrupt event handling. An
interrupt event awakens the system from each of the various operating modes and returns with the RETI
instruction to the mode that was selected before the interrupt event. The clocks used are ACLK and MCLK.
ACLK is the crystal frequency and MCLK is a multiple of ACLK and is used as the system clock.
The software can configure five operating modes:
Active mode (AM). The CPU is enabled with different combinations of active peripheral modules.
Low power mode 0 (LPM0). The CPU is disabled, peripheral operation continues, ACLK and MCLK signals
are active, and loop control for MCLK is active.
Low power mode 1 (LPM1). The CPU is disabled, peripheral operation continues, ACLK and MCLK signals
are active, and loop control for MCLK is inactive.
Low power mode 2 (LPM2). The CPU is disabled, peripheral operation continues, ACLK signal is active,
and MCLK and loop control for MCLK are inactive.
Low power mode 3 (LPM3). The CPU is disabled, peripheral operation continues, ACLK signal is active,
MCLK and loop control for MCLK are inactive, and the dc generator for the digital controlled oscillator (DCO)
(
MCLK generator) is switched off.
Low power mode 4 (LPM4). The CPU is disabled, peripheral operation continues, ACLK signal is inactive
(crystal oscillator stopped), MCLK and loop control for MCLK are inactive, and the dc generator for the DCO
is switched off.
The special function registers (SFR) include module-enable bits that stop or enable the operation of the specific
peripheral module. All registers of the peripherals may be accessed if the operational function is stopped or
enabled. However, some peripheral current-saving functions are accessed through the state of local register
bits. An example is the enable/disable of the analog voltage generator in the LCD peripheral, which is turned
on or off using one register bit.
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