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SBSLITE Telecom Standard Product Data Sheet
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010883, Issue 2
66
As each message arrives, the CRC-16 and valid bit is checked; if the valid bit is not set the
message is discarded, if it fails the CRC check it is flagged as being in error and an interrupt is
generated if enabled. If the CRC-16 is OK, regardless of the valid bit, the Page Link, User and
Aux bits are passed on immediately. If the FIFO erroneously overflows, an interrupt is generated.
10.19 Microprocessor Interface
The Microprocessor Interface block provides normal and test mode registers, and logic required
to connect to the microprocessor interface. The normal mode registers are required for normal
operation, and test mode registers are used to enhance testability of the SBSLITE.
Address
Register
000H
SBSLITE Master Reset
001H
SBSLITE Master Configuration
002H
SBSLITE Revision/Part Number
003H
SBSLITE Part Number/Manufacturer ID
004H
SBSLITE Master Bypass
005H
SBSLITE Master SPE Control #1
006H
SBSLITE Master SPE Control #2
007H
SBSLITE Receive Synchronization Delay
008H
SBSLITE In-Band Link User Bits
009H – 00FH
SBSLITE Reserved
010H
SBSLITE Master Interrupt Source
011H
SBSLITE Interrupt Register
012H
SBSLITE Interrupt Enable Register
013H
SBSLITE Loopback Configuration
014H
SBSLITE Master Clock Monitor #1, Accumulation Trigger
015H
SBSLITE Master Clock Monitor #2
016H
SBSLITE Master Interrupt Enable Register
017H
SBSLITE Free User Register
020H
ISTA Incoming Parity Configuration
021H
ISTA Incoming Parity Status
022H
ISTA TelecomBus Configuration
023H
ISTA Reserved
024H – 027H
Reserved
028H
IMSU Configuration
029H
IMSU Interrupt Status and Memory Page Update
02AH
IMSU Indirect Time Switch Address
02BH
IMSU Indirect Time Switch Data
02CH – 02FH
Reserved
030H
ICASM CAS Enable Indirect Address
031H
ICASM CAS Enable Indirect Control
032H
ICASM CAS Enable Indirect Data