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SBSLITE Telecom Standard Product Data Sheet
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010883, Issue 2
205
Register 0B0H: TW8E Control and Status
Bit
Type
Function
Default
Bit 15
Unused
X
Bit 14
Unused
X
Bit 13
Unused
X
Bit 12
Unused
X
Bit 11
Unused
X
Bit 10
Unused
X
Bit 9
Unused
X
Bit 8
Unused
X
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
R/W
Reserved
0
Bit 4
R/W
FIFOERRE
0
Bit 3
R/W
TPINS
0
Bit 2
R/W
Reserved
0
Bit 1
W
CENTER
0
Bit 0
R/W
DLCV
0
This register provides control and reports the status of the TW8E.
DLCV
The diagnose line code violation bit (DLCV) controls the insertion of line code violation in
the working transmit serial data stream. When this bit is set high, the encoded data is
inverted to generate the complementary running disparity.
CENTER
The FIFO centering control bit (CENTER) controls the separation of the FIFO read and write
pointers. CENTER is a write only bit. When a logic high is written to CENTER, and the
current FIFO depth is not in the range of 3, 4 or 5 characters, the FIFO depth is forced to be
four 8B/10B characters deep, with a momentary data corruption. Writing to the CENTER bit
when the FIFO depth is in the 3, 4 or 5 character range produces no effect. CENTER always
returns a logic low when read.
This bit must be set once CSU lock has been achieved.
TPINS
The Test Pattern Insertion (TPINS) controls the insertion of test pattern in the working
transmit serial data stream for jitter testing purpose. When this bit is set high, the test pattern
stored in the registers (TP[9:0]) is used to replace all the overhead and payload bytes of the
transmit data stream. When TPINS is set low, no test pattern is inserted.