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SBSLITE Telecom Standard Product Data Sheet
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010883, Issue 2
118
Register 04AH: OMSU Indirect Time Switch Address
Bit
Type
Function
Default
Bit 15
R/W
RWB
0
Bit 14
Unused
0
Bit 13
R/W
OUT_BYTE[13]
0
Bit 12
R/W
OUT_BYTE[12]
0
Bit 11
R/W
OUT_BYTE[11]
0
Bit 10
R/W
OUT_BYTE[10]
0
Bit 9
R/W
OUT_BYTE[9]
0
Bit 8
R/W
OUT_BYTE[8]
0
Bit 7
R/W
OUT_BYTE[7]
0
Bit 6
R/W
OUT_BYTE[6]
0
Bit 5
R/W
OUT_BYTE[5]
0
Bit 4
R/W
OUT_BYTE[4]
0
Bit 3
R/W
OUT_BYTE[3]
0
Bit 2
R/W
OUT_BYTE[2]
0
Bit 1
R/W
OUT_BYTE[1]
0
Bit 0
R/W
OUT_BYTE[0]
0
This register provides the address and the read/write control for the time switch configuration
ram. Writing to this register triggers a ram access. Note that when an indirect write access is to
be performed, the Indirect Time Switch Data register must first be setup before writing to this
register. There must be a minimum of 4 SYSCLK cycles between consecutive ram accesses. For
a ram read access, it will take a maximum of 8 SYSCLK cycles for the Indirect Time Switch Data
Register to contain valid data.
RWB
The indirect access control bit (RWB) selects between a write or read access to the time
switch configuration RAM. Writing a logic zero to RWB triggers and indirect write
operation. Data to be written is taken from the Indirect Time Switch Data register. Writing a
logic one to RWB triggers an indirect read operation. The read data can be found in the
Indirect Time Switch Data Register.
OUT_BYTE[13:0]
The OUT_BYTE[13:0] bits indicate the ram address to be accessed. Each address in the ram
corresponds to a location in the output data bus. The contents stored in each ram address
points to the byte from the input data bus which is to be output. In DS0 mode, legal values
are 000H to 25F7H (0 to 9719). In column mode, legal values are 000H to 437H (0 to 1079).
The byte numbers of the output frame are shown in the following table.