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參數(shù)資料
| 型號(hào)： | PM7383-PI |
| 廠商： | PMC-Sierra, Inc. |
| 英文描述： | FRAME ENGINE AND DATA LINK MANAGER 32A256 |
| 中文描述： | 框架引擎和數(shù)據(jù)鏈路管理32A256 |
| 文件頁(yè)數(shù)： | 62/231頁(yè) |
| 文件大?。?/td> | 1947K |
| 代理商： | PM7383-PI |
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RELEASED
DATASHEET
PM7383 FREEDM-32A256
ISSUE 1
PMC-2010336
FRAME ENGINE AND DATA LINK MANAGER 32A256
PROPRIETARY AND CONFIDENTIAL
54
The RAPI256 provides packet status information on the Rx APPI at the end of
every packet transfer. The RAPI256 asserts RERR at the end of packet
reception (REOP high) to indicate that the packet is in error. The RAPI256 may
be programmed to overwrite RXDATA[7:0] of the final word of each packet
transfer (REOP is high) with the status of packet reception when that packet is
errored (RERR is high). Overwriting of status information is enabled by setting
the STATEN bit in the RAPI Control register.
8.5.2 Polling Control and Management
The RAPI256 only responds to device polls which match the base address
programmed in the RAPI256 Control register. A positive poll response indicates
that at least one of the two FIFOs has a complete XFER[3:0] plus one blocks of
data, or an end of packet, and is ready to be selected to transfer this data across
the Rx APPI.
8.6 Transmit Any-PHY Interface
The Transmit Any-PHY Interface (TAPI256) provides a low latency path for
transferring data from the Transmit Any-PHY Packet Interface (Tx APPI) into the
partial packet buffer in the THDL256. The TAPI256 contains a FIFO block for
latency control as well as to segregate the APPI timing domain from the SYSCLK
timing domain. The TAPI256 contains the necessary logic to manage and respond
to channel polling from an upper layer device.
8.6.1 FIFO Storage and Control
The FIFO block temporarily stores channel data during transfer across the Tx
APPI. TAPI256 burst data transfers are transaction based on the writer side of
the FIFO – all data must be completely read from the FIFO before any further
data will be written into the FIFO. To support as close as possible to full Tx APPI
bus rate, a double buffer is used. While data is being read from the one FIFO,
data can be written into the other FIFO. Because the bandwidth on the reader
side of the FIFOs is higher than that on the writer side, the TAPI256 will not incur
any bandwidth reduction to maximum burst data transfers through its FIFOs.
The upper layer device cannot interrupt data transfers on the Tx APPI. However,
the FREEDM-32A256 may throttle the upper layer device if both FIFOs in the
TAPI256 are full. When the FIFOs in the TAPI256 cannot accept data, the
TAPI256 deasserts the TRDY output to the upper layer device connected to the
Tx APPI. In this instance, the upper layer device must halt data transfer until the
TRDY output is returned high. The upper layer device connected to the Tx APPI
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| PM7384 | Frame Engine and Data Link Manager |
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| PM7385 | Frame Engine and Data Link Manager |
| PM7385-BI | 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER WITH ANY-PHY PACKET INTERFACE |
| PM7388 | Frame Engine and Datalink Manager |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PM7384 | 制造商:PMC 制造商全稱:PMC 功能描述:Frame Engine and Data Link Manager |
| PM7384-BI | 制造商:PMC 制造商全稱:PMC 功能描述:FRAME ENGINE AND DATA LINK MANAGER 84P672 |
| PM7385 | 制造商:PMC 制造商全稱:PMC 功能描述:Frame Engine and Data Link Manager |
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