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參數(shù)資料
| 型號(hào)： | PM7383-PI |
| 廠商： | PMC-Sierra, Inc. |
| 英文描述： | FRAME ENGINE AND DATA LINK MANAGER 32A256 |
| 中文描述： | 框架引擎和數(shù)據(jù)鏈路管理32A256 |
| 文件頁(yè)數(shù)： | 16/231頁(yè) |
| 文件大?。?/td> | 1947K |
| 代理商： | PM7383-PI |
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RELEASED
DATASHEET
PM7383 FREEDM-32A256
ISSUE 1
PMC-2010336
FRAME ENGINE AND DATA LINK MANAGER 32A256
PROPRIETARY AND CONFIDENTIAL
8
slots (N x DS0) up to a maximum of 24 concatenated time-slots for a T1/J1 link
and 31 concatenated time-slots for an E1 link. Time-slots assigned to any
particular channel need not be contiguous within the T1/J1 or E1 link.
For unchannelised links, the FREEDM-32A256 processes up to 32 bi-directional
HDLC channels within 32 independently timed links. The links can be of arbitrary
frame format. When limited to three unchannelised links, each link can be rated
at up to 51.84 MHz provided SYSCLK is running at 45 MHz. For lower rate
unchannelised links, the FREEDM-32A256 processes up to 32 links each rated
at up to 10 MHz. In this case, the aggregate clock rate of all the links is limited to
64 MHz.
The FREEDM-32A256 supports mixing of up to 32 channelised T1/J1/E1,
unchannelised and H-MVIP links. The total number of channels in each direction
is limited to 256. The aggregate instantaneous clock rate over all 32 possible
links is limited to 64 MHz.
The FREEDM-32A256 provides a low latency “Any-PHY” packet interface (APPI)
to allow an external controller direct access into the 32 Kbyte partial packet
buffers. Up to seven FREEDM-32A256 devices may share a single APPI. For
each of the transmit and receive APPI, the external controller is the master of
each FREEDM-32A256 device sharing the APPI from the point of view of device
selection. The external controller is also the master for channel selection in the
transmit direction. In the receive direction, however, each FREEDM-32A256
device retains control over selection of its respective channels. The transmit and
receive APPI is made up of three groups of functional signals – polling, selection
and data transfer. The polling signals are used by the external controller to
interrogate the status of the transmit and receive 32 Kbyte partial packet buffers.
The selection signals are used by the external controller to select a FREEDM-
32A256 device, or a channel within a FREEDM-32A256 device, for data transfer.
The data transfer signals provide a means of transferring data across the APPI
between the external controller and a FREEDM-32A256 device.
In the receive direction, polling and selection are done at the device level.
Polling is not decoupled from selection, as the receive address pins serve as
both a device poll address and to select a FREEDM-32A256 device. In response
to a positive poll, the external controller may select that FREEDM-32A256 device
for data transfer. Once selected, the FREEDM-32A256 prepends an in-band
channel address to each partial packet transfer across the receive APPI to
associate the data with a channel. A FREEDM-32A256 must not be selected
after a negative poll response.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PM7384 | Frame Engine and Data Link Manager |
| PM7384-BI | FRAME ENGINE AND DATA LINK MANAGER 84P672 |
| PM7385 | Frame Engine and Data Link Manager |
| PM7385-BI | 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER WITH ANY-PHY PACKET INTERFACE |
| PM7388 | Frame Engine and Datalink Manager |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PM7384 | 制造商:PMC 制造商全稱:PMC 功能描述:Frame Engine and Data Link Manager |
| PM7384-BI | 制造商:PMC 制造商全稱:PMC 功能描述:FRAME ENGINE AND DATA LINK MANAGER 84P672 |
| PM7385 | 制造商:PMC 制造商全稱:PMC 功能描述:Frame Engine and Data Link Manager |
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