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參數(shù)資料
| 型號(hào)： | PM7385 |
| 廠商： | PMC-Sierra, Inc. |
| 英文描述： | Frame Engine and Data Link Manager |
| 中文描述： | 幀引擎和數(shù)據(jù)鏈接管理器 |
| 文件頁數(shù)： | 1/2頁 |
| 文件大小： | 48K |
| 代理商： | PM7385 |
PMC-1991025 (r2)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
2001
PMC-Sierra, Inc.
PM7385
PMC-Sierra,Inc.
Frame Engine and Data Link Manager
FREEDM-84A672
FEATURES
Single-chip multi-channel HDLC
controller with a 50 MHz, 16 bit Any-
PHY Packet Interface (APPI) for
transfer of packet data using an
external controller.
Supports up to 672 bi-directional
HDLC channels assigned to a
maximum of 84 channelised or
unchannelised links conveyed via a
19.44 MHz Scalable Bandwidth
Interconnect (SBI) interface.
Data on the SBI interface is divided
into three Synchronous Payload
Envelopes (SPEs). Each SPE can be
configured independently to carry data
for either 28 T1/J1 links, 21 E1 links, or
one unchannelised DS-3 link.
Supports three bi-directional HDLC
channels each assigned to an
unchannelised link with arbitrary rate
link of up to 51.84 MHz when SYSCLK
is running at 45 MHz. Each link may be
configured individually to replace one
of the SPEs conveyed on the SBI
interface.
For each channel, the HDLC receiver
supports programmable flag sequence
detection, bit de-stuffing and frame
check sequence validation. The
receiver supports the validation of both
CRC-CCITT and CRC-32 frame check
sequences.
For each channel, the HDLC
transmitter supports programmable
flag sequence generation, bit stuffing
and frame check sequence generation.
The transmitter supports the
generation of both CRC-CCITT and
CRC-32 frame check sequences. The
transmitter also aborts packets under
the direction of the external controller
or automatically when the channel
underflows.
Provides 32 Kbytes of on-chip memory
for partial packet buffering in both the
transmit and the receive directions.
This memory may be configured to
support a variety of different channel
configurations from a single channel
with 32 Kbytes of buffering to 672
channels, each with a minimum of 48
bytes of buffering.
Provides a 16 bit microprocessor
interface for configuration and status
monitoring.
Provides a standard five signal
P1149.1 JTAG test port for boundary
scan board test purposes.
Supports 3.3 Volt tolerant I/O.
352 pin enhanced ball grid array
(SBGA) package.
APPLICATIONS
PPP interfaces for routers.
Internet/Edge Routers.
Frame Relay/Multiservice Switches.
Packet-based DSLAM equipment.
Remote Access Concentrators.
Multiservice Access Concentrators.
DDATA[7:0]
DPL
DV5
DDP
SBI
Extract
SBI
Insert
Transmit HDLC
Processor/Partial
Packet Buffer
(THDL672)
Performance
Monitor
(PMON)
ADATA[7:0]
APL
AV5
ADP
AJUST_REQ
AACTIVE
ADETECT[1:0]
Receive
Channel
Assigner
(RCAS672)
Transmit
Channel
Assigner
(TCAS672)
Receive
HDLC Processor/
Partial Packet Buffer
(RHDL672)
TCLK[2:0]
TD [2:0]
JTAG
T
T
T
T
T
RD[2:0]
RCLK[2:0]
S
S
S
R
F
C
C
Microprocessor
Interface
W
C
A
A
D
I
R
Transmit Any-
PHY Packet
Interface
(TAPI672)
TXADDR[12:0]
TPA1[2:0]
TPA2[2:0]
TRDY
TXDATA[15:0]
TXPRTY
TSX
TEOP
TMOD
TERR
TXCLK
Receive Any-
PHY Packet
Interface
(RAPI672)
RXADDR[2:0]
RPA
RENB
RXDATA[15:0]
RXPRTY
RSX
REOP
RMOD
RERR
RVAL
RXCLK
R
S
P
BLOCK DIAGRAM
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PM7385-BI | 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER WITH ANY-PHY PACKET INTERFACE |
| PM7388 | Frame Engine and Datalink Manager |
| PM7389 | Frame Engine and Datalink Manager |
| PM7800 | Digital Correction Signal Processor |
| PM7830 | Baseband Radio Interface Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PM7385-BI | 制造商:PMC-Sierra 功能描述: |
| PM7386-BI | 制造商:Rochester Electronics LLC 功能描述: 制造商:PMC-Sierra 功能描述: |
| PM7388 | 制造商:PMC 制造商全稱:PMC 功能描述:Frame Engine and Datalink Manager |
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