
RELEASED 
DATASHEET 
PM7383 FREEDM-32A256
ISSUE 1 
PMC-2010336 
FRAME ENGINE AND DATA LINK MANAGER 32A256 
PROPRIETARY AND CONFIDENTIAL 
95
LINK[4:0]: 
The indirect link number bits (LINK[4:0]) select amongst the 32 receive links 
to be configured or interrogated in the indirect access. 
Reserved: 
The reserved bits must be set low for correct operation of the FREEDM-
32A256 device. 
RWB: 
The indirect access control bit (RWB) selects between a configure (write) or 
interrogate (read) access to the channel provision RAM.  The address to the 
channel provision RAM is constructed by concatenating the TSLOT[4:0] and 
LINK[4:0] bits.  Writing a logic zero to RWB triggers an indirect write 
operation.  Data to be written is taken from the PROV, the CDLBEN and the 
CHAN[7:0] bits of the RCAS Indirect Channel Data register.  Writing a logic 
one to RWB triggers an indirect read operation.  Addressing of the RAM is the 
same as in an indirect write operation.  The data read can be found in the 
PROV, the CDLBEN and the CHAN[7:0] bits of the RCAS Indirect Channel 
Data register. 
BUSY: 
The indirect access status bit (BUSY) reports the progress of an indirect 
access.  BUSY is set high when this register is written to trigger an indirect 
access, and will stay high until the access is complete.  At which point, BUSY 
will be set low.  This register should be polled to determine when data from an 
indirect read operation is available in the RCAS Indirect Channel Data register 
or to determine when a new indirect write operation may commence.