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DATA SHEET
PM7367 FREEDM-32P32
ISSUE 2
PMC-1991499
FRAME ENGINE AND DATA LINK MANAGER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE
73
1. PCI Host Accessible registers (PA) - these registers can be accessed through
the PCI Host interface.
2. PCI Configuration registers (PC) - these register can only be accessed
through the PCI Host interface during a PCI configuration cycle.
The PCI registers are addressable on dword boundaries only. The PCI offset
shown in the table below must be combined with a base address to form the PCI
Interface address. The base address can be found in the FREEDM-32P32
Memory Base Address register in the PCI Configuration memory space.
Table 12 – Normal Mode PCI Host Accessible Register Memory Map
PCI Offset
Register
0x000
FREEDM-32P32 Master Reset
0x004
FREEDM-32P32 Master Interrupt Enable
0x008
FREEDM-32P32 Master Interrupt Status
0x00C
FREEDM-32P32 Master Clock / BERT Activity Monitor and
Accumulation Trigger
0x010
FREEDM-32P32 Master Link Activity Monitor
0x014
FREEDM-32P32 Master Line Loopback #1
0x018
FREEDM-32P32 Master Line Loopback #2
0x01C
Reserved
0x020
FREEDM-32P32 Master BERT Control
0x024
FREEDM-32P32 Master Performance Monitor Control
0x028 - 0x03C
Reserved
0x040
GPIC Control
0x044 - 0x07C
GPIC Reserved
0x080 - 0x0FC
Reserved
0x100
RCAS Indirect Channel and Time-slot Select
0x104
RCAS Indirect Channel Data
0x108
RCAS Framing Bit Threshold
0x10C
RCAS Channel Disable
0x110 - 0x17C
RCAS Reserved
0x180
RCAS Link #0 Configuration