
DATA SHEET
PM7367 FREEDM-32P32
ISSUE 2
PMC-1991499
FRAME ENGINE AND DATA LINK MANAGER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE
262
Table 25 – Test Mode Register Memory Map
Address TA[10:0]
Register
0x000 - 0x7FC
Normal Mode Registers
0x800 - 0x83C
Reserved
0x840 - 0x87C
GPIC Test Registers
0x880 - 0x8FC
Reserved
0x900 - 0x9FC
RCAS Test Registers
0xA00 - 0xA3C
RHDL Test Registers
0xA40 - 0xA7C
Reserved
0xA80 - 0xAFC
RMAC Test Registers
0xB00 - 0xB7C
TMAC Test Registers
0xB80 - 0xBBC
THDL Test Registers
0xBC0 - 0xBFF
Reserved
0xC00 - 0xCFC
TCAS Test Registers
0xD00 - 0xD1C
PMON Test Registers
0xD20 - 0xFFF
Reserved
Notes on Test Mode Register Bits:
1. Writing values into unused register bits has no effect. However, to ensure
software compatibility with future, feature-enhanced versions of the product,
unused register bits must be written with logic zero. Reading back unused
bits can produce either a logic one or a logic zero; hence unused register bits
should be masked off by software when read.
2. Writable test mode register bits are not initialized upon reset unless otherwise
noted.
11.2 JTAG Test Port
The FREEDM-32P32 JTAG Test Access Port (TAP) allows access to the TAP
controller and the 4 TAP registers: instruction, bypass, device identification and
boundary scan. Using the TAP, device input logic levels can be read, device
outputs can be forced, the device can be identified and the device scan path can