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DATA SHEET
PM7367 FREEDM-32P32
ISSUE 2
PMC-1991499
FRAME ENGINE AND DATA LINK MANAGER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE
239
CEN:
The channelise enable bit (CEN) configures the corresponding transmit link
for channelised operation. TCLK[n] is held quiescent during the T1 framing
bit or the E1 framing byte. Thus, on the first rising edge of TCLK[n] after the
extended quiescent period, a downstream device can sample the m.s.b. of
time-slot 1. When CEN is set low, the corresponding link is unchannelised
and the E1 register bit is ignored. TCLK[n] is gapped during non-data bytes.
All data bits are treated as a contiguous stream with arbitrary byte alignment.
E1:
The E1 frame structure select bit (E1) configures the corresponding link for
channelised E1 operation when CEN is set high. TCLK[n] is held quiescent
during the FAS and NFAS framing bytes. The most significant bit of time-slot
1 is placed on TD[n] on the last falling edge of TCLK[n] ahead of the
extended quiescent period. Link data is present at time-slots 1 to 31. When
E1 is set low and CEN is set high, the corresponding link is configured for
channelised T1 operation. TCLK[n] is held quiescent during the framing bit.
The m.s.b. of time-slot 1 is placed on TD[n] on the last falling edge of
TCLK[n] ahead of the extended low period. Link data is present at time-slots
1 to 24. E1 is ignored when CEN is set low.