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DATA SHEET
PM7367 FREEDM-32P32
ISSUE 2
PMC-1991499
FRAME ENGINE AND DATA LINK MANAGER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE
124
CEN:
The channelise enable bit (CEN) configures the corresponding receive link for
channelised operation. RCLK[n] is held quiescent during the T1 framing bit
and the E1 framing bytes. The data bit on RD[n] clocked in by the first rising
edge of RCLK[n] after an extended quiescent period is considered to be the
most significant bit of time-slot 1. When CEN is set low, the corresponding
receive link is unchannelised. The E1 register bit is ignored. RCLK[n] is
gapped during non-data bytes. All data bits are treated as a contiguous
stream with arbitrary byte alignment.
E1:
The E1 frame structure select bit (E1) configures the corresponding receive
link for channelised E1 operation when CEN is set high. RCLK[n] is held
quiescent during the FAS and NFAS framing bytes. The data bit on RD[n]
clocked in by the first rising edge of RCLK[n] after an extended quiescent
period is considered to be the most significant bit of time-slot 1. Link data is
present at time-slots 1 to 31. When E1 is set low and CEN is set high, the
corresponding receive link is configured for channelised T1 operation.
RCLK[n] is held quiescent during the framing bit. The data bit on RD[n]
clocked in by the first rising edge of RCLK[n] after an extended quiescent
period is considered to be the most significant bit of time-slot 1. Link data is
present at time-slots 1 to 24. E1 is ignored when CEN is set low.