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參數(shù)資料
| 型號： | PM73488-PI |
| 廠商： | PMC-SIERRA INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 5 Gbit/s ATM Switch Fabric Element |
| 中文描述： | ATM SWITCHING CIRCUIT, PBGA596 |
| 封裝： | EPBGA-596 |
| 文件頁數(shù)： | 92/135頁 |
| 文件大?。?/td> | 1735K |
| 代理商： | PM73488-PI |
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PMC-Sierra, Inc.
PM73488 QSE
L
PMC-980616
Issue 3
5 Gbit/s ATMSwitch Fabric Element
Released
Datasheet
94
9.2
The QSE detects six classes of errors and each error in every class is reported using two bits:
Error_present: There is an error at the present moment
Error_latched: There was an error sometime in the past, between now and the last time this register was read.
Of these two bits, errors latched in the Error_latched registers can be further used to generate interrupts to the micro-
processor.
Note on Error Detection and Reporting
The six detected classes of errors fall into two categories:
Category 1: Errors that can be associated with an input or output port.
Errors in this category are only detected if the corresponding port is enabled.
Input port failed: This means that one of the SOC_IN or DATA_IN wires is stuck or glitchy. The
error_present register is at address 44-47, and the error_latched register is at address 48-4B. You can stop
checking for this error by turning off the appropriate input ports using the register at address 10-13.
BpAck failed: This means that one of the BPACK_IN wires is stuck or glitchy. The error_present register is
at address 4C-4F, and the error_latched register is at address 50-53. So you can stop checking for this error
by turning off the appropriate output port using the register at address 14-17.
Remote failure: This means that the downstream QSE did not sent a BP packet on some BPACK_IN wire
during some cell-time. By implication, it means that one of the SOC_OUT or DATA_OUT wires is stuck or
glitchy (to which the downstream QSE responds by withholding the BP packet). The error_present register
is at address 54-57, and the error_latched register is at address 58-5B. You can stop checking for this error
by turning off the appropriate output port using the register at address 14-17.
Parity error in a cell. The error_present register is at address 38-3B, and the error_latched register is at
address 3C-3F. You can stop checking for this error by turning off the appropriate input ports using the
register at address 10-13. A separate set of registers at address 40-43 allow you to disable interrupts due to
this error. You can also globally disable all parity checks on input ports using the CHIP_MODE register (bit
6).
Each of the above four classes of errors has a "summary" bit in the interrupt status register (ISR) at address 81. The
summary bit for a class is set if any enabled error is latched in that class. An actual interrupt to the microprocessor
(due to these classes of errors) will be generated if any of the four summary bits in the ISR are set and if the global
interrupt mask is enabled.
Category 2: Errors in this category are global to the entire chip.
CSTART is out of lock. The error_present register is at address 80 (bit 7), and the error_latched register is at
address 8A (bit 0). You can turn off the interrupt from this error using the register at address 80 (bit 6). If this
error is causing an interrupt, this is indicated by bit 4 of the ISR (address 81).
Parity error in external MC connection RAM. There is no error_present register. The error_latched register
is at address B(bit 6). You can turn off the parity check using the register at address B(bit 4) and you can
disable interrupts due to this error using address B(bit 5). This error will cause an interrupt if it has been
latched and if interrupts from this error have not been disabled using the register at address B (bit 5).
9.3
Microprocessor Ports Bit Definitions
NOTE: The bits reset to
0
b
unless otherwise indicated.
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| PM73488 | 5 Gbit/s ATM Switch Fabric Element |
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