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PMC-Sierra, Inc.
PM73488 QSE
L
PMC-980616
Issue 3
5 Gbit/s ATMSwitch Fabric Element
Released
Datasheet
111
10
JTAG
10.1
The QRT supports the IEEE Boundary Scan Specification as described in the IEEE 1149.1 standards. The Test
Access Port (TAP) consists of the five standard pins, TRSTB, TCK, TMS, TDI and TDO, used to control the TAP
controller and the boundary scan registers. The TRSTB input is the active low reset signal used to reset the TAP con-
troller. TCK is the test clock used to sample data on input, TDI and to output data on output, TDO. The TMS input
is used to direct the TAP controller through its states. The basic boundary scan architecture is shown below.
JTAG Support
Figure 42. Boundary Scan Architecture
The boundary scan architecture consists of a TAP controller, an instruction register with instruction decode, a bypass
register, a device identification register and a boundary scan register. The TAP controller interprets the TMS input
and generates control signals to load the instruction and data registers. The instruction register with instruction
decode block is used to select the test to be executed and/or the register to be accessed. The bypass register offers a
Boundary Scan
Register
Control
TDI
TDO
Device Identification
Register
Bypass
Register
Instruction
Register
and
Decode
TRSTB
TMS
TCK
Test
Access
Port
Controller
Mux
DFF
Select
Tri-state Enable