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S/UNI-JET Data Sheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
260
Set the S/UNI-JET Transmit Cell Processor block built in set test (BIST) controls signals by
writing:
°
10000000 to test register 480H
°
10000000 to test register 580H
°
10000000 to test register 680H
°
10000000 to test register 780H
°
10101010 to test register 482H
°
10101010 to test register 582H
°
10101010 to test register 682H
°
10101010 to test register 782H
Toggle REF8KI (pin T3, datasheet page 29) signal several times. This provides the clock to
the RAM. REF8KI is the test clock used by the TXCP and RXCP blocks when in test mode.
Set IOTST (bit 2) in the Master Test Register (datasheet pg. 291) to '0' (by writing 00000000
to Register 400H).
Resume normal device programming.
13.2
Register Settings for Basic Configurations
Table 33 Register Settings for Basic Configurations
Mode of
Operation
S/UNI-JET Registers (values in Hexadecimal)
300
302
303
304
308
30C
330
334
338
339
340
341
344
34C
360
361
380
39B
T3 C-bit ADM
C0
00
00
F8
00
00
83
01
--
--
--
--
--
--
04
04
04
00
T3 M23 ADM
C0
00
00
F8
00
00
82
00
--
--
--
--
--
--
04
04
04
00
T3 C-bit PLCP
40
00
00
F8
04
04
83
01
--
--
--
--
--
--
04
00
04
00
T3 M23 PLCP
40
00
00
F8
04
04
82
00
--
--
--
--
--
--
04
00
04
00
T3 C-bit framer
only
50
00
00
78
00
00
83
01
--
--
--
--
--
--
--
--
--
01
T3 M23 framer
only
50
00
00
78
00
00
82
00
--
--
--
--
--
--
--
--
--
01
E3 G.832 ADM
C0
40
40
F8
00
00
--
--
04
00
01
01
--
--
04
08
04
00
E3 G.832 framer
only
50
40
40
78
00
00
--
--
04
00
01
01
--
--
--
--
--
01
E3 G.751 ADM
C0
40
40
F8
00
44
--
--
00
00
00
41
--
--
04
08
04
00
E3 G.751 PLCP
40
40
40
F8
44
44
--
--
00
04
00
41
--
--
04
00
04
00
E3 G.751 framer
only
50
40
40
78
00
00
--
--
00
00
00
01
--
--
--
--
--
01
J2 ADM
J2 framer only
1
C0
80
80
F8
00
00
--
--
--
--
--
03
0E
04
08
04
00
50
80
80
78
00
00
--
--
--
--
--
03
0E
--
--
01
E1 PLCP
40
C0
C0
--
C4
C4
--
--
--
--
--
--
--
04
00
04
00
E1 ADM
40
C0
C0
--
C0
C0
--
--
--
--
--
--
--
04
00
04
00