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PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
PM7340 S/UNI-IMA-8
DATA SHEET
PMC-2001723
ISSUE 3
INVERSE MULTIPLEXING OVER ATM
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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10.6 Microprocessor Interface
The Microprocessor Interface Block provides the interrupt logic and an interface
to normal-mode registers contained within the design blocks. The normal mode
registers are required for normal operation.
10.6.1 Mapping and link identification
10.6.1.1
Clock/Data
The links are identified by sequential numbers from 0 to 7. In order to support
multiple fractional flows on a single physical link (up to a maximum of eight
fractional flows), the remapping feature may be used to split a single channelized
link into multiple virtual physical links. The mapped value is refered to as the
physical link ID from the perspective of the IMA Layer.
10.6.1.2
IMA
Within the IMA sublayer, mapping is performed between the physical link IDs and
the Any-PHY/UTOPIA L2 virtual PHY address. This mapping can be a one-to-one
relationship as for TC connections or it may be a many-to-one relationship as for
an IMA group.
The physical link to Virtual PHY mapping is independent in the RX and TX
directions.
The selection of the RX VPHY ID in Any-PHY or single port UTOPIA L2 mode is
unconstrained as this ID exists only as a prepend. In multiple port UTOPIA L2
mode, the RX VPHY ID must be a unique value between 0 and 3 for each flow.
The selection of the TX VPHY ID is limited by the following rules:
All groups must have a unique value between 0 to 3.
Note: The actual address used on the Any-PHY bus to access a particular channel is
a combination of the TX VPHY ID (bits 2:0), which TCAEN bit is set(bits 6:3), and
the Tx Any-PHY Address Config Reg(bits 15:7).