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PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
PM7340 S/UNI-IMA-8
DATA SHEET
PMC-2001723
ISSUE 3
INVERSE MULTIPLEXING OVER ATM
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
84
1. The RDAT, which reads and writes cell and status information. The granularity of
access by the RDAT is a concatenated 1-cell write, 1-cell read. Either the write or the
read may not be performed, depending on the RDATs requirements.
2. The microprocessor interface, which performs diagnostic reading or writing of 64
bytes of data. This data is aligned with the cell data. This access is only allowed
when the SDRAM is placed in Diagnostic mode and is provided to enable SDRAM
testing. While it is in diagnostic mode, all regular accesses from the RDAT are
disabled
3. The refresh controller, which has a programmable refresh rate.
The SDRAM interface will perform the initialization sequence for the SDRAM.
This sequence is triggered by the SDRAM enable bit in the SDRAM control
register. The sequence will program the SDRAM with a CAS latency of 3,
sequential access, write burst mode, and a burst length of 8. Applications should
ensure that sufficient time is provided between SDRAM power up and when this
enable bit is set.
10.3 Link FIFOs
In the transmit direction, per link FIFOs exist to provide an elastic store to ensure
proper operation. The number of cells in the FIFO at any particular time varies
as a function of the CDV introduced by the insertion of stuff cells and ICP cells,
the effects of the physical link interface, and the smoothing of data from the ATM
layer for group level CDV. During operation, these FIFOs are loaded a cell at a
time and emptied in a TDM fashion. The Link FIFOs in the transmit direction are
8 cells deep.
In the receive direction, the link FIFOs serve as an interface between the TDM
domain and the ATM cell domain. Cells are gathered in the FIFO for each link
and then burst out to the external memory by the RDAT. The Link FIFOs in the
receive direction are 2 cells deep.
A diagnostic loopback capability is provided to loopback data from the receive
link FIFOs to the transmit link FIFO; this will loopback all links when enabled.