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PM7329 S/UNI-APEX-1K800
DATASHEET
PMC-2010141
ISSUE 2
ATM TRAFFIC MANAGER AND SWITCH
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
49
10
FUNCTIONAL DESCRIPTION
This section describes the function of each entity in the S/UNI-APEX-1K800 block
diagram. In this document, receive and transmit are used with the S/UNI-APEX-
1K800 as the frame of reference. For example, receive is used to describe data
paths which are coming into the device.
10.1 Any-PHY Interfaces
The S/UNI-APEX-1K800 Interface are Any-PHY compliant 8/16-bit master/slave
interface for both Loop and WAN ports. The loop and WAN interfaces are
configured independently. Both interfaces are fully compatible with the following
Any-PHY options:
Any-PHY master.
UTOPIA L2 master (UL2M).
UTOPIA L1 master (UL1M).
UTOPIA L2 slave (UL2S).
10.1.1 Receive Interface
The S/UNI-APEX-1K800 requires a 2-byte Ingress Connection Identifier (ICI) that
uses the 10 LSB (least significant bits). The ICI is received with every cell and
uniquely identifies the VCC or VPC. The ICI can be received within the HEC/UDF
field (16bit I/F only), as a user prepend, or encoded within the VPI/VCI field. In
Any-PHY mode, an address prepend is expected to be in the first word/byte of
every cell. Inclusion of optional words/bytes are statically configured for the
interface.
The Receive Cell Transfer Format is shown in Figure 4 and Figure 5.
Figure 4
- 16bit Receive Cell Transfer Format
Bits 15-8
Bits 7-0
Word 0
(Any-PHY
only)
Word 1
(Optional)
Address Prepend
User Prepend
Word 2
H1
H2
Word 3
H3
H4
Word 4
(Optional)
HEC/UDF