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參數(shù)資料
| 型號(hào)： | PM7329-BI |
| 廠商： | PMC-SIERRA INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | ATM TRAFFIC MANAGER AND SWITCH |
| 中文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, PBGA352 |
| 封裝： | 35 X 35 MM, 1.45 MM HEIGHT, SBGA-352 |
| 文件頁(yè)數(shù)： | 26/232頁(yè) |
| 文件大?。?/td> | 1585K |
| 代理商： | PM7329-BI |
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PM7329 S/UNI-APEX-1K800
DATASHEET
PMC-2010141
ISSUE 2
ATM TRAFFIC MANAGER AND SWITCH
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
12
7
DESCRIPTION
The PM7329 S/UNI-APEX-1K800 is a full duplex ATM traffic management
device, providing cell switching, per VC queuing, traffic shaping, congestion
management, and hierarchical scheduling to up to 128 loop ports and up to 4
WAN ports.
The S/UNI-APEX-1K800 provides per-VC queuing for 1024 VCs. A per-VC
queue may be allocated to any Class of Service (COS), within any port, in either
direction (ingress or egress path). Per-VC queuing enables PCR or SCR per-VC
shaping on WAN ports and greater fairness of bandwidth allocation between VCs
within a COS.
The S/UNI-APEX-1K800 provides three level hierarchical scheduling for port,
COS, and VC level scheduling. There are two, three level schedulers; one for the
loop ports and one for the WAN ports. The three level scheduler for the WAN
ports provides:
Weighted Interleaved Round Robin (WIRR) scheduling across the 4 WAN
ports enabling selectability of bandwidth allocation between the ports.
Priority Fair scheduling across the 4 COS’s within each port. This class
scheduler is a modified priority scheduler allowing minimum bandwidth
allocations to lower priority classes within the port. Class scheduling within
a port is independent of activity on all other ports.
There are three types of VC schedulers. VC scheduling within a class is
independent of activity on all other classes
Shaped fair queuing is available for 4 classes. If the COS is shaped,
each VC within the class is scheduled for emission based on its VCs
shaping rate. During class congestion, the VC scheduler may lower a
VCs rate in proportion to a normalization factor calculated as a function
of the VCs rate and the aggregate rate of all active VCs within the
class.
Weighted Fair Queuing in which weights are used to provide fairness
between the VCs within a class.
Frame continuous scheduling where an entire packet is accumulated
prior to transferring to a class queue.
The three-level scheduler for the loop ports provides:
Weighted Interleaved Round Robin (WIRR) scheduling across the 128
loop ports enabling selectability of bandwidth allocation between the ports
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| PM7340-PI | SCREW,WING |
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相關(guān)代理商/技術(shù)參數(shù) |
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| PM733 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| PM7339 | 制造商:PMC 制造商全稱:PMC 功能描述:SATURN USER NETWORK INTERFACE CELL DELINEATION BLOCK |
| PM734 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| PM7340 | 制造商:PMC 制造商全稱:PMC 功能描述:S/UNI INVERSE MULTIPLEXING FOR ATM, 8 LINKS |
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