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STANDARD PRODUCT
PMC-Sierra, Inc.
PM6344 EQUAD
PMC-951013
ISSUE 5
QUADRUPLE E1 FRAMER
ix
FIGURE 23
- TYPICAL DATA FRAME .....................................................................................197
FIGURE 24
- RFDL NORMAL DATA AND ABORT SEQUENCE.............................................198
FIGURE 25
- RFDL FIFO OVERRUN......................................................................................199
FIGURE 26
- XFDL NORMAL DATA SEQUENCE...................................................................200
FIGURE 27
- XFDL UNDERRUN SEQUENCE.......................................................................201
FIGURE 28
- PAYLOAD LOOPBACK ......................................................................................202
FIGURE 29
- LINE LOOPBACK ..............................................................................................203
FIGURE 30
- DIAGNOSTIC DIGITAL LOOPBACK .................................................................204
FIGURE 31
- RECEIVE BACKPLANE INTERFACE WITH RCLKOSEL = 1............................209
FIGURE 32
- LCV COUNT VS. BER........................................................................................211
FIGURE 33
- FER COUNT VS. BER .......................................................................................211
FIGURE 34
- CRCE COUNT VS. BER ....................................................................................212
FIGURE 35
- MICROPROCESSOR READ ACCESS TIMING................................................221
FIGURE 36
- MICROPROCESSOR WRITE ACCESS TIMING...............................................223
FIGURE 37
- BACKPLANE TRANSMIT INPUT TIMING DIAGRAM .......................................225
FIGURE 38
- BACKPLANE TRANSMIT INPUT TIMING DIAGRAM .......................................226
FIGURE 39
- XCLK=37.056 MHZ INPUT TIMING ..................................................................227
FIGURE 40
- TCLKI INPUT TIMING........................................................................................228
FIGURE 41
- DIGITAL RECEIVE INTERFACE INPUT TIMING DIAGRAM.............................229
FIGURE 42
- TRANSMIT DATA LINK INPUT TIMING DIAGRAM...........................................230
FIGURE 43
- BACKPLANE RECEIVE TIMING DIAGRAM......................................................231
FIGURE 44
- BACKPLANE RECEIVE TIMING (RCLKOSEL = 1) DIAGRAM.........................232
FIGURE 45
- MULTIPLEXED BACKPLANE RECEIVE TIMING DIAGRAM............................233
FIGURE 46
- RECEIVE DATA LINK OUTPUT TIMING DIAGRAM..........................................234