參數(shù)資料
型號： PID9q-604e
廠商： IBM Microeletronics
英文描述： 32-Bit RISC Microprocessor(32位精簡指令集微處理器)
中文描述： 32位RISC微處理器（32位精簡指令集微處理器）
文件頁數(shù)： 8/29頁
文件大?。?/td> 543K
代理商： PID9Q-604E
8
PID9q-604e Hardware Datasheet
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
IBM
Table 5 provides the power consumption for the 604e.
1.4.2 AC Electrical Characteristics
This section provides the AC electrical characteristics for the 604e. These specifications are for
250, 300, 333 and 350 MHz processor core frequencies. The processor core frequency is
determined by the bus (SYSCLK) frequency and the settings of the PLL_CFG[0–3] signals. All
timings are specified respective to the rising edge of SYSCLK.
1.4.2.1 Clock AC Specifications
Table 6 provides the clock AC timing specifications as defined in Figure 1.
Table 5. Power Consumption
CPU Clock:
SYSCLK
Processor Core Frequency
Unit
250 MHz
300 MHz
333 MHz
350 MHz
Full-On Mode
Typical
Maximum
6.0
6.8
7.5
8.0
W
10.6
12.0
13.4
14.5
W
Nap Mode
Maximum
0.80
0.80
0.82
0.84
W
Notes:
1. These values apply for all valid PLL_CFG[0–3] settings and do not include output driver power (OVdd) or
analog supply power (AVdd). OVdd power is system dependent but is typically
≤
10% of Vdd. Worst-case
AVdd = 15 mW.
2. Typical power is an average value estimated at Vdd = AVdd = 1.9 V, OVdd = 3.3 V, T
j
= 25 °C in a system
executing typical applications and benchmark sequences. Typical power numbers should be used in
planning for proper thermal management.
3. Maximum power is estimated at Vdd = AVdd = 2.0 V, OVdd = 3.465 V,T
j
= 0 °C using a worst-case
instruction mix. These values should be used for power supply design.
4. Nap mode power consumption is estimated, and assumes no snoop activity.
Table 6. Clock AC Timing Specifications
Vdd = AVdd = 1.9 ±100 mV dc, OVdd = 3.3
±
5% V dc, GND = 0 V dc, 0
≤
T
j
≤
105 °C
Num
Characteristic
250 MHz
300 MHz
333 MHz
350 MHz
Unit
Notes
Min
Max
Min
Max
Min
Max
Min
Max
Processor frequency
200
250
250
300
283
333
300
350
MHz
1
VCO frequency
400
500
500
600
566
666
600
700
MHz
1
SYSCLK frequency
28.6
100
35.7
100
40.4
100
42.8
100
MHz
1, 6
1
SYSCLK cycle time
10
35
10
28
10
25
10
23
ns
2, 3
SYSCLK rise and fall time
1.0
2.0
1.0
2.0
1.0
2.0
1.0
2.0
ns
2
4
SYSCLK duty cycle
measured at 0.9 V
40
60
40
60
40
60
40
60
%
3
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