參數(shù)資料
型號(hào)： PID9q-604e
廠商： IBM Microeletronics
英文描述： 32-Bit RISC Microprocessor(32位精簡(jiǎn)指令集微處理器)
中文描述： 32位RISC微處理器（32位精簡(jiǎn)指令集微處理器）
文件頁(yè)數(shù)： 5/29頁(yè)
文件大?。?/td> 543K
代理商： PID9Q-604E
9/17/99 Revision 1.4
PID9q-604e Hardware Datasheet
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
5
5:1, 11:2, 6:1, 13:2, and 7:1)
— A 64-bit split-transaction external data bus with burst transfers
— Support for address pipelining and limited out-of-order bus transactions
— Four burst write queues—three for cache copyback operations and one for snoop push
operations
— Two single-beat write queues
— Additional signals and signal redefinition for direct-store operations
— Provides a data streaming mode that allows consecutive burst read data transfers to
occur without intervening dead cycles. This mode also disables data retry operations.
— No-DRTRY mode eliminates the DRTRY signal from the qualified bus grant and allows
read operations. This improves performance on read operations for systems that do
not use the DRTRY signal. No-DRTRY mode makes read data available to the
processor one bus clock cycle sooner than if normal mode is used.
Multiprocessing support features include the following:
— Hardware enforced, four-state cache coherency protocol (MESI) for data cache. Bits
are provided in the instruction cache to indicate only whether a cache block is valid or
invalid.
— Separate port into data cache tags for bus snooping
— Load/store with reservation instruction pair for atomic memory references,
semaphores, and other multiprocessor operations
Power management
— NAP mode supports full shut down and snooping
— Operating voltage of 1.9
±
100 mV
Performance monitor can be used to help in debugging system designs and improving
software efficiency, especially in multiprocessor systems.
In-system testability and debugging features through JTAG boundary-scan capability
1.3 General Parameters
The following list provides a summary of the general parameters of the 604e:
Technology
0.25 μm CMOS, five-layer metal
6.97 mm x 6.75mm (47 mm
2
)
Die size
Transistor count
5.1 million
Logic design
Fully-static
Package
Surface mount 255-lead ceramic ball grid array (CBGA)
Core power supply
1.9 V
±
100 mV dc
I/O power supply
3.3 V
±
5% V dc
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