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參數(shù)資料
| 型號： | PID9q-604e |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-Bit RISC Microprocessor(32位精簡指令集微處理器) |
| 中文描述： | 32位RISC微處理器（32位精簡指令集微處理器） |
| 文件頁數(shù)： | 22/29頁 |
| 文件大?。?/td> | 543K |
| 代理商： | PID9Q-604E |
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22
PID9q-604e Hardware Datasheet
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
IBM
1.8.2 Input and Output Signal Mode Selection
The PID9q-604e’s input buffers can be configured through the connection of the ARRAY_WR
signal to provide input hysteresis and enable the CLKOUT signal. If the ARRAY_WR signal is
connected to OVdd, the PID9q-604e will select the Hysteresis Off input buffer threshold mode, and
the CLKOUT signal is enabled, which is the default mode for this specification. When Hysteresis
OFF mode is selected the VM is 0.9V.
If ARRAY_WR is connected to GND, Hysteresis On mode is selected, and the CLKOUT signal is
placed in a high impedance state. When Hysteresis On mode is selected, the VM is 1.3V, and the
input transition points are 1.1V for V
IL
and 1.5V for V
IH
. Hysteresis On mode provides for greater
noise immunity on inputs, and the input hold time requirement for Low to High transitions is
increased.
When the ARRAY_WR signal is connected to the HRESET signal, Hysteresis On mode is
selected, and the CLKOUT signal is enabled. If the ARRAY_WR signal is connected to an inverted
HRESET signal, Hysteresis Off mode is selected, and the CLKOUT signal is placed in a high
impedance state.
Table 12 below shows the configuration of the ARRAY_WR signal to select input signal hysteresis
and enable the CLKOUT signal.
The PID9q-604e implements a Fast Out output mode which allows increased system bus
frequencies. The PID9q-604e can be configured for Fast Out mode by connecting the
L2_TSTCLK signal to GND or the HRESET signal. When Fast Out mode is enabled, the output
valid and output hold times are reduced. If the L2_TSTCLK signal is connected to OVdd or to an
inverted HRESET, compatibility mode is selected.
Table 12. Input Signal Hysteresis and CLKOUT Signal Configuration
Signal
Connected to
Mode Selected
Notes
ARRAY_WR
OVdd
Hyteresis Off
CLKOUT Enabled
1
GND
Hyteresis On
CLKOUT high impedance
HRESET signal
Hyteresis On
CLKOUT Enabled
HRESET
Hyteresis Off
CLKOUT high impedance
2
Notes:
1. Default Mode
2.HRESET is the inverted state of the HRESET signal
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