參數(shù)資料
型號(hào)： PID9q-604e
廠商： IBM Microeletronics
英文描述： 32-Bit RISC Microprocessor(32位精簡(jiǎn)指令集微處理器)
中文描述： 32位RISC微處理器（32位精簡(jiǎn)指令集微處理器）
文件頁數(shù)： 11/29頁
文件大?。?/td> 543K
代理商： PID9Q-604E
9/17/99 Revision 1.4
PID9q-604e Hardware Datasheet
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
11
Figure 3 provides the mode select input timing diagram for the 604e.
Figure 3. Mode Select Input Timing Diagram
1.4.2.3 Output AC Specifications
The output specifications of the 604e for both driving high and driving low depend on the
capacitive loading on each output and the drive capability enabled for that output. Additionally, the
timing specifications for outputs driving low also depend on the voltage swing required to drive to
0.4V. Table 8 provides the output AC timing specifications for a 5pF, 50 W
transmission line load.
In order to derive the actual timing specifications for a given set of conditions, it is recommended
that IBIS simulation models be used. The IBIS models are currently based on device simulation
data. Compatibility mode specifications are provided to support PID9q-604e use in existing
designs. Contact the local IBM sales office for information on the availability of these models.
Table 8 provides the output AC timing specifications for the 604e (refer to Figure 4)
.
Table 8. Output AC Timing Specifications
1
Vdd = AVdd = 1.9
±
100 mV dc, OVdd = 3.3
=
±
5% V dc, GND = 0 V dc, 0
≤
T
j
≤
105 °C, drive mode [11]
6
Num
Characteristic
250, 300, 333, 350 MHz
Unit Notes
Min
Max
Compatibility
Mode
11
SYSCLK to output driven (output enable time)
0.75
—
0.75 Min
ns
2, 5
12
SYSCLK to TS, XATS, ARTRY, SHD, ABB and
DBB output valid
—
3.75
4.75 Max
ns
5
13
SYSCLK to all other signals output valid
—
4.75
5.75 Max
ns
5
14
SYSCLK to output invalid (output hold)
0.0
0.5 Min
ns
2, 5
15
SYSCLK to output high impedance (all signals
except ARTRY, SHD, ABB, DBB, TS, and
XATS)
—
3.4
4.4 Max
ns
5
16
SYSCLK to output high impedance TS, XATS
—
3.4
4.4 Max
ns
5
17
SYSCLK to ABB and DBB high impedance
after precharge
—
1.0* t
sysclk
1.0* t
sysclk
Max
ns
4
18
SYSCLK to ARTRY and SHD high impedance
before precharge
—
3.4
4.4 Max
ns
5
DRTRY
HRESET
VM
VM = Midpoint Voltage (0.9 V)
10
9
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