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參數(shù)資料
| 型號： | PID9q-604e |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-Bit RISC Microprocessor(32位精簡指令集微處理器) |
| 中文描述： | 32位RISC微處理器（32位精簡指令集微處理器） |
| 文件頁數(shù)： | 4/29頁 |
| 文件大小： | 543K |
| 代理商： | PID9Q-604E |
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PID9q-604e Hardware Datasheet
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
IBM
— Eight condition register (CR) rename buffers
Completion unit
— The completion unit retires an instruction from the 16-entry reorder buffer when all
instructions ahead of it have been completed and the instruction has finished
execution.
— Guarantees sequential programming model (precise exception model)
— Monitors all dispatched instructions and retires them in order
— Tracks unresolved branches and flushes executed, dispatched, and fetched
instructions if branch is mispredicted
— Retires as many as four instructions per clock
Separate on-chip instruction and data caches (Harvard architecture)
— 32-Kbyte, four-way set-associative instruction and data caches
— LRU replacement algorithm
— 32-byte (eight-word) cache block size
— Physically indexed/physical tags. (Note that the PowerPC architecture refers to
physical address space as real address space.)
— Cache write-back or write-through operation programmable on a per page or per block
basis
— Instruction cache can provide four instructions per clock; data cache can provide two
words per clock
— Caches can be disabled in software
— Caches can be locked
— Parity checking performed on both caches
— Data cache coherency (MESI) maintained in hardware
— Secondary data cache support provided
— Instruction cache coherency maintained in hardware
— Data cache line-fill buffer forwarding. In the 604 only the critical double word of the
cache block was made available to the requesting unit at the time it was burst into the
line-fill buffer. Subsequent data was unavailable until the cache block was filled. On the
604e, subsequent data is also made available as it arrives in the line-fill buffer.
Separate memory management units (MMUs) for instructions and data
— Address translation facilities for 4-Kbyte page size, variable block size, and 256-Mbyte
segment size
— Both TLBs are 128-entry and two-way set associative
— TLBs are hardware reloadable (that is, the page table search is performed in hardware)
— Separate IBATs and DBATs (four each) also defined as SPRs
— Separate instruction and data translation lookaside buffers (TLBs)
— LRU replacement algorithm
— 52-bit virtual address; 32-bit physical address
Bus interface features include the following:
— Selectable processor-to-bus clock frequency ratios (1:1, 3:2, 2:1, 5:2, 3:1, 7:2, 4:1, 9:2,
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