參數(shù)資料
型號(hào)： PIC30F2010
廠商： Microchip Technology Inc.
英文描述： dsPIC High-Performance 16-bit Digital Signal Controller Family Overview
中文描述： dsPIC數(shù)字信號(hào)的高性能16位數(shù)字信號(hào)控制器系列簡(jiǎn)介
文件頁(yè)數(shù)： 30/34頁(yè)
文件大?。?/td> 500K
代理商： PIC30F2010
dsPIC30F
DS70025D-page 30
Advance Information
2001 Microchip Technology Inc.
6.10.7
I
2
C 7-BIT SLAVE MODE
OPERATION
Once enabled (I2CEN = 1), the slave module will wait
for a start bit to occur (IDLE_MODE). Following a start-
bit detect, 8 bits are shifted into I2CRSR and the
address is compared against I2CADD. In 7-bit mode,
bits I2CADD<6:0> are compared against bits
I2CRSR<7:1> and bit0 is the R/W bit. All incoming bits
are sampled with the rising edge of SCL.
If the address matches, an acknowledge will be sent,
and on the falling edge of the ninth bit (ACK bit) the
i2c_int_flag interrupt is set.
6.10.7.1
Slave Mode Transmission
If R/W bit received is a
’
1
’
then the serial port will go into
’
XMIT_MODE
’
. It will send ACK on the ninth bit and
then hold SCL to
’
0
’
until the CPU responds by writing
to I2CTRN. SCL is released and 8 bits of data are
shifted out. Data bits are shifted out on the falling edge
of SCL such that SDA is valid during SCL high (see tim-
ing diagram). Interrupt is set on the falling edge of the
ninth clock pulse.
The ACK bit from master is latched on the ninth clock
pulse. If ACK = 1 then
’
XMIT_MODE
’
ends and the
serial port resumes
’
IDLE_MODE
’
looking for another
start bit.
If ACK = 0, then it will again hold SCL low until I2CTRN
is full (i.e., written to).
TBF status flag:
During transmit, the TBF bit
(I2CSTAT<0>) is set when the CPU writes to I2CTRN,
and TBF is cleared in hardware when all 8 bits are
shifted out.
IWCOL status flag:
If the user attempts to write a byte
to the I2CTRN register when TBF = 1 (i.e., I2CTRN is
still shifting out previous data byte), then IWCOL is set.
IWCOL must be cleared in software.
R/W status flag:
Latches and holds the R/W bit
received following the last address-match.
6.11
Controller Area Network Module
(CAN)
The Controller Area Network (CAN) is a serial commu-
nications protocol which efficiently supports distributed
real-time control with a very high level of security.
Figure 6-11 shows a block diagram of a CAN module.
The DSC CAN module satisfies the Version 2.0B spec-
ification, which allows message identifier lengths of 11
and/or 29 bits to be used (an identifier length of 29 bits
allows over 536 Million message identifiers). Version
2.0B CAN is also referred to as "Extended CAN".
6.11.1
CAN MODULE FEATURES
The CAN module is a communication controller imple-
menting the CAN 2.0 A/B protocol as defined in the
BOSCH specification. The module will support CAN
1.2, CAN 2.0A, CAN2.0B Passive, and CAN 2.0B
Active versions of the protocol. The module implemen-
tation is a Full CAN system. Based on requirements
expressed by CAN application software authors for
predictable real-time behavior and the need to mini-
mize silicon and to save cost, the module implements
an advanced buffer arrangement.
Note:
Following a RESTART condition in 10-bit
mode, the user only needs to match the
first 7-bit address.
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