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參數資料
| 型號： | PIC30F2010 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | dsPIC High-Performance 16-bit Digital Signal Controller Family Overview |
| 中文描述： | dsPIC數字信號的高性能16位數字信號控制器系列簡介 |
| 文件頁數： | 2/34頁 |
| 文件大?。?/td> | 500K |
| 代理商： | PIC30F2010 |
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dsPIC30F
DS70025D-page 2
Advance Information
2001 Microchip Technology Inc.
Selectable oscillator options, including:
- 4X/8X/16X Phase Lock Loop (of primary
oscillator)
- Secondary Oscillator (32 kHz) clock input
(Timer1)
- High speed internal RC oscillator
In-Circuit Serial Programming
(ICSP
) via 3
pins and power/ground
CMOS Technology:
Low-power, high-speed FLASH technology
Fully static design
Wide operating voltage range (2.5V to 5.5V)
Industrial and extended temperature ranges
Low power consumption
Packaging:
100-pin TQFP
64-pin TQFP
40-pin DIP, 44-pin TQFP
28-pin DIP (300 mil.), 28-pin SSOP
1.0
CPU CORE ARCHITECTURAL
DESCRIPTION
The dsPIC30F Digital Signal Controller is a modified
Harvard Architecture core with a 16-bit datapath and a
24-bit wide instruction memory. The dsPIC30F core
seamlessly integrates the superior control attributes of
a 16-bit MCU and the computation power of a DSP.
The dsPIC30F instruction set adds many enhance-
ments to the previous PICMicro Microcontroller (MCU)
instruction sets, while maintaining an easy migration
path from these PICMicro MCU platforms.
1.1
Core Overview
The core has a 24-bit instruction word, with a variable
length opcode field. The PC (program counter) is 23
bits wide (with the LS-bit always clear, see Figure 1-3
and Table 1-1), addressing up to 4M long words (24
bits). An PIC18C-like instruction prefetch mechanism is
used to help maintain throughput. Deeper levels of
pipelining have been intentionally avoided to maintain
good real-time performance. Unconditional overhead
free program loop constructs are supported using the
DO and REPEAT instructions, both of which are inter-
ruptable at any point.
The working register array is comprised of 16 x 16-bit
registers, each of which can act as data, address or off-
set registers. One working register (W15) operates as
the software stack pointer for interrupts and calls.
The data space is 32K words of word or byte address-
able space, which is split into two blocks referred to as
X and Y data memory. Each block has its own indepen-
dent Address Generation Unit (AGU). Most instructions
operate solely through the X memory AGU which will
make it appear as one linear space encompassing all
data space (X and Y). The MAC class of DSP instruc-
tions will operate through both the X and Y AGUs, split-
ting the data address space into two parts (see
Section 1.2.1). The X and Y data space boundary is
arbitrary and defined through the address decode of
each memory array.
The upper 32K bytes of data space memory can option-
ally be mapped into program space at any 16K pro-
gram word boundary defined by the 8-bit Data Space
Program PAGE (DSPPAG) register. This lets any
instruction access program space as if it were data
space (other than the additional access cycle it con-
sumes), plus it allows external RAM hooked onto the
external program space bus to be mapped into data
space, effectively providing an external data space
path.
Overhead free circular buffers (modulo addressing) are
supported in both X and Y address spaces. They are
intended to remove the loop overhead for DSP algo-
rithms, but X modulo addressing can be universally
applied using any instructions.
The X AGU also supports bit reverse addressing to
greatly simplify input or output data reordering for radix-
2 FFT algorithms.
The Instruction Set Architecture (ISA) has been signifi-
cantly enhanced beyond that of the PIC18C, but main-
tains an acceptable level of backward compatibility. All
PIC18C instructions and addressing modes are sup-
ported either directly or through simple macros. Many
of the ISA enhancements have been driven by compiler
efficiency needs (see Section 1.1.1).
The core supports inherent (no operand), relative, lit-
eral, memory direct and 3 groups of addressing modes
(MODE1, MODE2 and MODE3) for register direct and
register indirect modes. There are 11 addressing
modes in total, plus some special varients for DSP
instruction. Instructions are associated with predefined
addressing modes depending upon their functional
requirements. Please refer to the Instruction Set
Description document [DS70026n_C] for more details.
For most instructions, the core is capable of executing
a data (or program data) memory read, a working reg-
ister (data) read, a data memory write and a program
(instruction) memory read per instruction cycle. As a
result, 3 operand instructions can be supported, allow-
ing A+B=C operations to be executed in a single cycle.
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