
PIC18F85J11 FAMILY
DS39774C-page 390
Preliminary
2007 Microchip Technology Inc.
I
2
C Stop Condition Receive or
Transmit Mode .................................................210
MSSP I
2
C Bus Data .................................................368
MSSP I
2
C Bus Start/Stop Bits .................................368
Parallel Slave Port (PSP) Read ...............................146
Parallel Slave Port (PSP) Write ...............................145
PWM Output ............................................................169
Repeated Start Condition .........................................206
Reset, Watchdog Timer (WDT), Oscillator Start-up
Timer (OST) and Power-up Timer (PWRT) .....359
Send Break Character Sequence ............................231
Slave Synchronization .............................................179
Slow Rise Time (MCLR Tied to V
DD
,
V
DD
Rise > T
PWRT
) ............................................49
SPI Mode (Master Mode) .........................................178
SPI Mode (Slave Mode, CKE = 0) ...........................180
SPI Mode (Slave Mode, CKE = 1) ...........................180
Synchronous Reception
(Master Mode, SREN) ..............................234, 248
Synchronous Transmission ..............................232, 246
Synchronous Transmission
(Through TXEN) .......................................233, 247
Time-out Sequence on Power-up
(MCLR Not Tied to V
DD
), Case 1 .......................49
Time-out Sequence on Power-up
(MCLR Not Tied to V
DD
), Case 2 .......................49
Time-out Sequence on Power-up
(MCLR Tied to V
DD
, V
DD
Rise < T
PWRT
) ...........48
Timer0 and Timer1 External Clock ..........................360
Transition for Entry to Idle Mode ................................42
Transition for Entry to SEC_RUN Mode ....................39
Transition for Entry to Sleep Mode ............................41
Transition for Two-Speed Start-up
(INTRC to HSPLL) ...........................................281
Transition for Wake From Idle to Run Mode ..............42
Transition for Wake From Sleep (HSPLL) .................41
Transition From RC_RUN Mode to
PRI_RUN Mode .................................................40
Transition From SEC_RUN Mode to
PRI_RUN Mode (HSPLL) ..................................39
Transition to RC_RUN Mode .....................................40
Timing Diagrams and Specifications
Capture/Compare/PWM Requirements
(CCP1, CCP2) .................................................361
CLKO and I/O Requirements ...................................358
EUSART/AUSART Synchronous Receive
Requirements ...................................................370
EUSART/AUSART Synchronous Transmission
Requirements ...................................................370
Example SPI Mode Requirements
(Master Mode, CKE = 0) .................................. 362
Example SPI Mode Requirements
(Master Mode, CKE = 1) .................................. 363
Example SPI Mode Requirements
(Slave Mode, CKE = 0) .................................... 364
Example SPI Slave Mode
Requirements (CKE = 1) ................................. 365
External Clock Requirements .................................. 356
I
2
C Bus Data Requirements (Slave Mode) .............. 367
I
2
C Bus Start/Stop Bits Requirements
(Slave Mode) ................................................... 366
Internal RC Accuracy ............................................... 357
MSSP I
2
C Bus Data Requirements ......................... 369
MSSP I
2
C Bus Start/Stop Bits Requirements .......... 368
PLL Clock ................................................................ 357
Reset, Watchdog Timer, Oscillator Start-up
Timer, Power-up Timer and Brown-out
Reset Requirements ........................................ 359
Timer0 and Timer1 External
Clock Requirements ........................................ 360
Top-of-Stack Access .......................................................... 61
TSTFSZ ........................................................................... 325
Two-Speed Start-up ................................................. 271, 281
Two-Word Instructions
Example Cases .......................................................... 65
V
V
DDCORE
/V
CAP
Pin .......................................................... 279
Voltage Reference Specifications .................................... 353
Voltage Regulator (On-Chip) ........................................... 279
Brown-out Reset (BOR) ........................................... 280
Low-Voltage Detection (LVD) .................................. 279
Operation in Sleep Mode ......................................... 280
Power-up Requirements .......................................... 280
W
Watchdog Timer (WDT) ........................................... 271, 278
Associated Registers ............................................... 278
Control Register ....................................................... 278
Programming Considerations .................................. 278
WCOL ...................................................... 205, 206, 207, 210
WCOL Status Flag ................................... 205, 206, 207, 210
WWW Address ................................................................ 391
WWW, On-Line Support ...................................................... 5
X
XORLW ............................................................................ 325
XORWF ........................................................................... 326