
2007 Microchip Technology Inc.
Preliminary
DS39774C-page 381
PIC18F85J11 FAMILY
INDEX
A
A/D ...................................................................................251
A/D Converter Interrupt, Configuring .......................255
Acquisition Requirements ........................................256
ADCAL Bit ................................................................259
ADCON0 Register ....................................................251
ADCON1 Register ....................................................251
ADCON2 Register ....................................................251
ADRESH Register ............................................251, 254
ADRESL Register ....................................................251
Analog Port Pins, Configuring ..................................257
Associated Registers ...............................................259
Automatic Acquisition Time ......................................257
Configuring the Module ............................................255
Conversion Clock (T
AD
) ...........................................257
Conversion Requirements .......................................372
Conversion Status (GO/DONE Bit) ..........................254
Conversions .............................................................258
Converter Calibration ...............................................259
Converter Characteristics ........................................371
Operation in Power-Managed Modes ......................259
Special Event Trigger (CCP2) ..................................258
Use of the CCP2 Trigger ..........................................258
Absolute Maximum Ratings .............................................339
AC (Timing) Characteristics .............................................354
Load Conditions for Device Timing
Specifications ...................................................355
Parameter Symbology .............................................354
Temperature and Voltage
Specifications ...................................................355
Timing Conditions ....................................................355
ACKSTAT ........................................................................207
ACKSTAT Status Flag .....................................................207
ADCAL Bit ........................................................................259
ADCON0 Register ............................................................251
GO/DONE Bit ...........................................................254
ADCON1 Register ............................................................251
ADCON2 Register ............................................................251
ADDFSR ..........................................................................328
ADDLW ............................................................................291
Addressable Universal Synchronous Asynchronous
Receiver Transmitter (AUSART). See AUSART.
ADDULNK ........................................................................328
ADDWF ............................................................................291
ADDWFC .........................................................................292
ADRESH Register ............................................................251
ADRESL Register ....................................................251, 254
Analog-to-Digital Converter. See A/D.
ANDLW ............................................................................292
ANDWF ............................................................................293
Assembler
MPASM Assembler ..................................................336
AUSART
Asynchronous Mode ................................................242
Associated Registers, Receive ........................245
Associated Registers, Transmit .......................243
Receiver ...........................................................244
Setting up 9-Bit Mode with
Address Detect ........................................244
Transmitter .......................................................242
Baud Rate Generator (BRG) ................................... 240
Associated Registers ....................................... 240
Baud Rate Error, Calculating ........................... 240
Baud Rates, Asynchronous Modes ................. 241
High Baud Rate Select (BRGH Bit) ................. 240
Operation in Power-Managed Modes .............. 240
Sampling ......................................................... 240
Control Registers ..................................................... 237
Synchronous Master Mode ...................................... 246
Associated Registers, Receive ........................ 248
Associated Registers, Transmit ....................... 247
Reception ........................................................ 248
Transmission ................................................... 246
Synchronous Slave Mode ........................................ 249
Associated Registers, Receive ........................ 250
Associated Registers, Transmit ....................... 249
Reception ........................................................ 250
Transmission ................................................... 249
Auto-Wake-up on Sync Break Character ......................... 230
B
Baud Rate Generator ...................................................... 203
BC .................................................................................... 293
BCF ................................................................................. 294
BF .................................................................................... 207
BF Status Flag ................................................................. 207
Block Diagrams
16-Bit Byte Select Mode ............................................ 99
16-Bit Byte Write Mode .............................................. 97
16-Bit Word Write Mode ............................................ 98
8-Bit Multiplexed Mode ............................................ 101
A/D ........................................................................... 254
Analog Input Model .................................................. 255
AUSART Receive .................................................... 244
AUSART Transmit ................................................... 242
Baud Rate Generator .............................................. 203
Capture Mode Operation ......................................... 166
Comparator Analog Input Model .............................. 265
Comparator I/O Operating Modes ........................... 262
Comparator Output .................................................. 264
Comparator Voltage Reference ............................... 268
Comparator Voltage Reference
Output Buffer Example .................................... 269
Compare Mode Operation ....................................... 167
Connections for On-Chip Voltage Regulator ........... 279
Device Clock .............................................................. 29
EUSART Receive .................................................... 228
EUSART Transmit ................................................... 226
External Power-on Reset Circuit
(Slow V
DD
Power-up) ........................................ 47
Fail-Safe Clock Monitor ........................................... 282
Generic I/O Port Operation ...................................... 123
Interrupt Logic .......................................................... 108
MSSP (I
2
C Master Mode) ........................................ 201
MSSP (I
2
C Mode) .................................................... 182
MSSP (SPI Mode) ................................................... 173
On-Chip Reset Circuit ................................................ 45
PIC18F6XJ11 ............................................................ 10
PIC18F8XJ11 ............................................................ 11
PLL ............................................................................ 34