參數(shù)資料
型號： PIC16F77
廠商： Microchip Technology Inc.
英文描述： 40-Pin 8-Bit CMOS FLASH Microcontrollers(40腳、8位CMOS 閃速微控制器)
中文描述： 40引腳8位CMOS閃存微控制器（40腳，8位的CMOS閃速微控制器）
文件頁數(shù)： 79/170頁
文件大小： 3150K
代理商： PIC16F77
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 79
PIC16F7X
10.2.2
USART ASYNCHRONOUS RECEIVER
The receiver block diagram is shown in Figure 10-4.
The data is received on the RC7/RX/DT pin and drives
the data recovery block. The data recovery block is
actually a high speed shifter operating at x16 times the
baud rate, whereas the main receive serial shifter oper-
ates at the bit rate, or at F
OSC
.
Once Asynchronous mode is selected, reception is
enabled by setting bit CREN (RCSTA<4>).
The heart of the receiver is the receive (serial) shift reg-
ister (RSR). After sampling the STOP bit, the received
data in the RSR is transferred to the RCREG register (if
it is empty). If the transfer is complete, flag bit RCIF
(PIR1<5>) is set. The actual interrupt can be enabled/
disabled
by
setting/clearing
(PIE1<5>). Flag bit RCIF is a read only bit which is
cleared by the hardware. It is cleared when the RCREG
register has been read and is empty. The RCREG is a
double buffered register (i.e., it is a two deep FIFO). It
enable
bit
RCIE
is possible for two bytes of data to be received and
transferred to the RCREG FIFO and a third byte to
begin shifting to the RSR register. On the detection of
the STOP bit of the third byte, if the RCREG register is
still full, the overrun error bit OERR (RCSTA<1>) will be
set. The word in the RSR will be lost. The RCREG reg-
ister can be read twice to retrieve the two bytes in the
FIFO. Overrun bit OERR has to be cleared in software.
This is done by resetting the receive logic (CREN is
cleared and then set). If bit OERR is set, transfers from
the RSR register to the RCREG register are inhibited
and no further data will be received, therefore, it is
essential to clear error bit OERR if it is set. Framing
error bit FERR (RCSTA<2>) is set if a STOP bit is
detected as clear. Bit FERR and the 9th receive bit are
buffered the same way as the receive data. Reading
the RCREG will load bits RX9D and FERR with new
values, therefore, it is essential for the user to read the
RCSTA register before reading RCREG register, in
order not to lose the old FERR and RX9D information.
FIGURE 10-4: USART RECEIVE BLOCK DIAGRAM
FIGURE 10-5: ASYNCHRONOUS RECEPTION
x64 Baud Rate CLK
SPBRG
Baud Rate Generator
RC7/RX/DT
Pin Buffer
and Control
SPEN
Data
Recovery
CREN
OERR
FERR
RSR Register
MSb
LSb
RX9D
RCREG Register
FIFO
Interrupt
RCIF
RCIE
Data Bus
8
STOP
START
(8)
7
1
0
RX9
F
OSC
÷
64
÷
16
or
START
bit
bit7/8
bit1
bit0
bit7/8
bit0
STOP
bit
START
bit
START
bit
bit7/8
STOP
bit
RX (pin)
Rcv Buffer reg
reg
Read Rcv
Buffer reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
WORD 1
RCREG
WORD 2
RCREG
STOP
bit
Note:
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set. An overrun error indicates an error in user firmware.
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PIC16F777-E/PT 功能描述:8位微控制器 -MCU 14kBF 368RM 36I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC16F777-I/ML 功能描述:8位微控制器 -MCU 14KB 368 RAM 36 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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