參數(shù)資料
型號： PIC16F77
廠商： Microchip Technology Inc.
英文描述： 40-Pin 8-Bit CMOS FLASH Microcontrollers(40腳、8位CMOS 閃速微控制器)
中文描述： 40引腳8位CMOS閃存微控制器（40腳，8位的CMOS閃速微控制器）
文件頁數(shù)： 53/170頁
文件大小： 3150K
代理商： PIC16F77
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 53
PIC16F7X
7.0
TIMER2 MODULE
Timer2 is an 8-bit timer with a prescaler and a
postscaler. It can be used as the PWM time base for the
PWM mode of the CCP module(s). The TMR2 register
is readable and writable, and is cleared on any device
RESET.
The input clock (F
OSC
/4) has a prescale option of 1:1,
1:4
or
1:16,
selected
T2CKPS1:T2CKPS0 (T2CON<1:0>).
The Timer2 module has an 8-bit period register, PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon RESET.
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit
TMR2IF, (PIR1<1>)).
Timer2 can be shut off by clearing control bit TMR2ON
(T2CON<2>) to minimize power consumption.
Register 7-1 shows the Timer2 control register.
Additional information on timer modules is available in
the PICmicro
Mid-Range MCU Family Reference
Manual (DS33023).
by
control
bits
7.1
Timer2 Prescaler and Postscaler
The prescaler and postscaler counters are cleared
when any of the following occurs:
a write to the TMR2 register
a write to the T2CON register
any device RESET (POR, MCLR Reset, WDT
Reset or BOR)
TMR2 is not cleared when T2CON is written.
7.2
Output of TMR2
The output of TMR2 (before the postscaler) is fed to the
SSP module, which optionally uses it to generate shift
clock.
FIGURE 7-1:
TIMER2 BLOCK DIAGRAM
REGISTER 7-1:
T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)
Comparator
TMR2
Output
(1)
Sets Flag
bit TMR2IF
TMR2 reg
Reset
Postscaler
1:1
to
Prescaler
1:1, 1:4, 1:16
PR2 reg
2
F
OSC
/4
1:16
EQ
4
Note 1:
TMR2 register output can be software selected by the
SSP module as a baud clock.
T2OUTPS3:
T2OUTPS0
T2CKPS1:
T2CKPS0
U-0
—
R/W-0
TOUTPS3
R/W-0
TOUTPS2
R/W-0
TOUTPS1
R/W-0
TOUTPS0
R/W-0
TMR2ON T2CKPS1 T2CKPS0
R/W-0
R/W-0
bit 7
bit 0
bit 7
bit 6-3
Unimplemented:
Read as
‘
0
’
TOUTPS3:TOUTPS0
: Timer2 Output Postscale Select bits
0000
= 1:1 Postscale
0001
= 1:2 Postscale
0010
= 1:3 Postscale
1111
= 1:16 Postscale
TMR2ON
: Timer2 On bit
1
= Timer2 is on
0
= Timer2 is off
T2CKPS1:T2CKPS0
: Timer2 Clock Prescale Select bits
00
= Prescaler is 1
01
= Prescaler is 4
1x
= Prescaler is 16
bit 2
bit 1-0
Legend:
R = Readable bit
- n = Value at POR reset
W = Writable bit
’
1
’
= Bit is set
U = Unimplemented bit, read as
‘
0
’
’
0
’
= Bit is cleared
x = Bit is unknown
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