
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 163
PIC16F7X
Section ...............................................................45
T0CKI .................................................................46
Timer1
Asynchronous Counter Mode ............................51
Capacitor Selection ............................................51
Operation in Timer Mode ...................................50
Oscillator ............................................................51
Prescaler ............................................................51
Resetting of Timer1 Registers ...........................51
Resetting Timer1 using a CCP Trigger Output ..51
Synchronized Counter Mode .............................50
T1CON ...............................................................49
TMR1H ..............................................................51
TMR1L ...............................................................51
Timer2
Block Diagram ...................................................53
Postscaler ..........................................................53
Prescaler ............................................................53
T2CON ...............................................................53
Timing Diagrams
Brown-out Reset ......................................................134
Capture/Compare/PWM ...........................................136
CLKOUT and I/O ......................................................133
I
2
C Reception (7-bit Address) ....................................69
Power-up Timer .......................................................134
Reset ........................................................................134
SPI Master Mode .......................................................65
SPI Slave Mode (CKE = 1) ........................................65
SPI Slave Mode Timing (CKE = 0) ............................65
Start-up Timer ..........................................................134
Time-out Sequence on Power-up ....................103, 104
Timer0 ......................................................................135
Timer1 ......................................................................135
USART Asynchronous Master Transmission .............78
USART Asynchronous Reception ..............................79
USART Synchronous Receive .................................143
USART Synchronous Reception ................................85
USART Synchronous Transmission ..................83, 143
Wake-up from SLEEP via Interrupt ..........................109
Watchdog Timer .......................................................134
Timing Diagrams and Specifications
A/D Conversion ........................................................145
I
2
C Bus Data ............................................................141
I
2
C Bus Start/Stop Bits .............................................140
TMR0 .................................................................................17
TMR0 Register ...................................................................15
TMR1CS bit .......................................................................49
TMR1H ...............................................................................17
TMR1H Register ................................................................15
TMR1L ...............................................................................17
TMR1L Register .................................................................15
TMR1ON bit .......................................................................49
TMR2 .................................................................................17
TMR2 Register ...................................................................15
TMR2ON bit .......................................................................53
TOUTPS0 bit ......................................................................53
TOUTPS1 bit ......................................................................53
TOUTPS2 bit ......................................................................53
TOUTPS3 bit ......................................................................53
TRISA ................................................................................17
TRISA Register ..................................................................16
TRISB ................................................................................17
TRISB Register ..................................................................16
TRISC ................................................................................17
TRISC Register ..................................................................16
TRISD ................................................................................ 17
TRISD Register .................................................................. 16
TRISE ................................................................................ 17
TRISE Register ............................................................ 16, 35
IBF Bit ........................................................................ 36
IBOV Bit ..................................................................... 36
PSPMODE Bit ............................................... 34, 35, 38
TXREG .............................................................................. 17
TXSTA ............................................................................... 17
TXSTA Register ................................................................. 73
SYNC Bit ............................................................. 73, 74
TRMT Bit ................................................................... 73
TX9 Bit ....................................................................... 73
TX9D Bit .................................................................... 73
TXEN Bit .............................................................. 73, 89
U
UA ...................................................................................... 62
Universal Synchronous Asynchronous Receiver Transmitter.
See
USART
Update Address bit, UA ..................................................... 62
USART .............................................................................. 73
Asynchronous Mode .................................................. 77
Receive Block Diagram ..................................... 81
Asynchronous Receiver ............................................. 79
Asynchronous Reception ........................................... 80
Asynchronous Transmitter ......................................... 77
Baud Rate Generator (BRG) ..................................... 75
Baud Rate Formula ........................................... 75
Baud Rates, Asynchronous Mode (BRGH=0) ... 76
Sampling ........................................................... 75
Mode Select (SYNC Bit) ...................................... 73, 74
Overrun Error (OERR Bit) .......................................... 74
RC6/TX/CK Pin ........................................................ 7, 8
RC7/RX/DT Pin ....................................................... 7, 8
RCSTA Register ........................................................ 74
Receive Block Diagram ............................................. 79
Serial Port Enable (SPEN Bit) ................................... 73
Single Receive Enable (SREN Bit) ............................ 74
Synchronous Master Mode ........................................ 82
Synchronous Master Reception ................................ 84
Synchronous Master Transmission ........................... 82
Synchronous Slave Mode .......................................... 86
Transmit Block Diagram ............................................ 77
Transmit Data, 9th Bit (TX9D) ................................... 73
Transmit Enable (TXEN Bit) ................................ 73, 89
Transmit Enable, Nine-bit (TX9 Bit) ........................... 73
Transmit Shift Register Status (TRMT Bit) ................ 73
TXSTA Register ......................................................... 73
W
Wake-up from SLEEP ................................................ 95, 108
Interrupts ......................................................... 101, 102
MCLR Reset ............................................................ 102
Timing Diagram ....................................................... 109
WDT Reset .............................................................. 102
Watchdog Timer (WDT) ............................................. 95, 107
Block Diagram ......................................................... 107
Enable (WDTE Bit) .................................................. 107
Postscaler.
See
Postscaler, WDT
Programming Considerations .................................. 107
RC Oscillator ........................................................... 107
Time-out Period ....................................................... 107
WDT Reset, Normal Operation .................. 99, 101, 102
WDT Reset, SLEEP .................................. 99, 101, 102
WCOL ................................................................................ 63