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  • 參數(shù)資料
    型號: PIC16F77
    廠商: Microchip Technology Inc.
    英文描述: 40-Pin 8-Bit CMOS FLASH Microcontrollers(40腳、8位CMOS 閃速微控制器)
    中文描述: 40引腳8位CMOS閃存微控制器(40腳,8位的CMOS閃速微控制器)
    文件頁數(shù): 51/170頁
    文件大?。?/td> 3150K
    代理商: PIC16F77
    2000 Microchip Technology Inc.
    Advance Information
    DS30325A-page 51
    PIC16F7X
    6.4
    Timer1 Operation in Asynchronous
    Counter Mode
    If control bit T1SYNC (T1CON<2>) is set, the external
    clock input is not synchronized. The timer continues to
    increment asynchronous to the internal phase clocks.
    The timer will continue to run during SLEEP and can
    generate an interrupt on overflow, which will wake-up
    the processor. However, special precautions in soft-
    ware are needed to read/write the timer (Section 6.4.1).
    In Asynchronous Counter mode, Timer1 can not be
    used as a time base for capture or compare operations.
    6.4.1
    READING AND WRITING TIMER1 IN
    ASYNCHRONOUS COUNTER MODE
    Reading TMR1H or TMR1L, while the timer is running
    from an external asynchronous clock, will guarantee a
    valid read (taken care of in hardware). However, the
    user should keep in mind that reading the 16-bit timer
    in two 8-bit values itself, poses certain problems since
    the timer may overflow between the reads.
    For writes, it is recommended that the user simply stop
    the timer and write the desired values. A write conten-
    tion may occur by writing to the timer registers, while
    the register is incrementing. This may produce an
    unpredictable value in the timer register.
    Reading the 16-bit value requires some care. Exam-
    ples 12-2 and 12-3 in the PICmicro
    Mid-Range MCU
    Family Reference Manual (DS33023) show how to
    read and write Timer1 when it is running in Asynchro-
    nous mode.
    6.5
    Timer1 Oscillator
    A crystal oscillator circuit is built-in between pins T1OSI
    (input) and T1OSO (amplifier output). It is enabled by
    setting control bit T1OSCEN (T1CON<3>). The oscilla-
    tor is a low power oscillator rated up to 200 kHz. It will
    continue to run during SLEEP. It is primarily intended
    for use with a 32 kHz crystal. Table 6-1 shows the
    capacitor selection for the Timer1 oscillator.
    The Timer1 oscillator is identical to the LP oscillator.
    The user must provide a software time delay to ensure
    proper oscillator start-up.
    TABLE 6-1:
    CAPACITOR SELECTION FOR
    THE TIMER1 OSCILLATOR
    6.6
    Resetting Timer1 using a CCP Trigger
    Output
    If the CCP1 or CCP2 module is configured in Compare
    mode
    to
    generate
    a
    (CCP1M3:CCP1M0 =
    1011
    ), this signal will reset
    Timer1.
    special
    event
    trigger
    Timer1 must be configured for either Timer or Synchro-
    nized Counter mode, to take advantage of this feature.
    If Timer1 is running in Asynchronous Counter mode,
    this RESET operation may not work.
    In the event that a write to Timer1 coincides with a spe-
    cial event trigger from CCP1 or CCP2, the write will
    take precedence.
    In this mode of operation, the CCPRxH:CCPRxL regis-
    ter pair effectively becomes the period register for
    Timer1.
    6.7
    Resetting of Timer1 Register Pair
    (TMR1H, TMR1L)
    TMR1H and TMR1L registers are not reset to 00h on a
    POR, or any other RESET, except by the CCP1 and
    CCP2 special event triggers.
    T1CON register is reset to 00h on a Power-on Reset or
    a Brown-out Reset, which shuts off the timer and
    leaves a 1:1 prescale. In all other RESETS, the register
    is unaffected.
    6.8
    Timer1 Prescaler
    The prescaler counter is cleared on writes to the
    TMR1H or TMR1L registers.
    Osc Type
    LP
    Freq
    32 kHz
    100 kHz
    200 kHz
    C1
    33 pF
    15 pF
    15 pF
    C2
    33 pF
    15 pF
    15 pF
    These values are for design guidance only.
    Crystals Tested:
    32.768 kHz
    Epson C-001R32.768K-A
    100 kHz
    Epson C-2 100.00 KC-P
    200 kHz
    STD XTL 200.000 kHz
    Note 1:
    Higher capacitance increases the stability of
    the oscillator, but also increases the start-up
    time.
    2:
    Since each resonator/crystal has its own
    characteristics, the user should consult the
    resonator/crystal manufacturer for appropri-
    ate values of external components.
    ± 20 PPM
    ± 20 PPM
    ± 20 PPM
    Note:
    The special event triggers from the CCP1
    and CCP2 modules will not set interrupt
    flag bit TMR1IF (PIR1<0>).
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