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參數資料
| 型號： | PI7C8150ND |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | 2-Port PCI-to-PCI Bridge |
| 中文描述： | 2端口PCI至PCI橋 |
| 文件頁數： | 87/106頁 |
| 文件大?。?/td> | 904K |
| 代理商： | PI7C8150ND |
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PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
77
August 22, 2002 – Revision 1.02
11
Clock 7 disable
R/W
If bit is 0, then S_CLKOUT [7] is enabled.
If bit is 1, then S_CLKOUT [7] is disabled and driven low.
If bit is 0, then S_CLKOUT [8] is enabled.
If bit is 1, then S_CLKOUT [8] is disabled and driven low.
If bit is 0, then S_CLKOUT [9] is enabled.
If bit is 1, then S_CLKOUT [9] is disabled and driven low.
Reserved. Returns 00 when read.
12
Clock 8 disable
R/W
13
Clock 9 disable
R/W
15:14
Reserved
RO
14.1.41
P_SERR_L STATUS REGISTER – OFFSET 68h
Bit
Function
Type
Description
1: Signal P_SERR_L was asserted because an address parity error
was detected on P or S bus.
16
Address Parity
Error
R/WC
Reset to 0
1: Signal P_SERR_L was asserted because a posted write data parity
error was detected on the target bus.
17
Posted Write
Data Parity Error
R/WC
Reset to 0
1: Signal P_SERR_L was asserted because the bridge was unable to
deliver post memory write data to the target after 2
attempts.
18
Posted Write
Non-delivery
R/WC
Reset to 0
1: Signal P_SERR_L was asserted because the bridge received a
target abort when delivering post memory write data.
19
Target Abort
during Posted
Write
R/WC
Reset to 0.
1: Signal P_SERR_L was asserted because the bridge received a
master abort when attempting to deliver post memory write data
20
Master Abort
during Posted
Write
R/WC
Reset to 0.
1: Signal P_SERR_L was asserted because the bridge was unable to
deliver delayed write data after 2
24
attempts.
21
Delayed Write
Non-delivery
R/WC
Reset to 0
1: Signal P_SERR_L was asserted because the bridge was unable to
read any data from the target after 2
attempts.
22
Delayed Read –
No Data from
Target
R/WC
Reset to 0.
1: Signal P_SERR_L was asserted because a master did not repeat a
read or write transaction before master timeout.
23
Delayed
Transaction
Master Timeout
R/WC
Reset to 0.
14.1.42
PORT OPTION REGISTER – OFFSET 74h
Bit
0
Function
Reserved
Type
R/O
Description
Reserved. Returns 0 when read. Reset to 0.
Controls PI7C8150’s detection mechanism for matching memory
read retry cycles from the initiator on the primary interface
1
Primary MEMR
Command Alias
Enable
R/W
0: exact matching for non-posted memory write retry cycles from
initiator on the primary interface
1: alias MEMRL or MEMRM to MEMR for memory read retry
cycles from the initiator on the primary interface
Reset to 0
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相關代理商/技術參數 |
參數描述 |
|---|---|
| PI7C8150ND-33 | 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 256-Pin BGA 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 256-Pin BGA 制造商:Pericom Semiconductor Corporation 功能描述:PCI BUS CONTROLLER, PBGA256 |
| PI7C8152 | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ENHANCED 2- PORT TO PCI BRIDGE INTEL 21152 COMPORISON |
| PI7C8152A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-Port PCI-to-PCI Bridge |
| PI7C8152A_07 | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-Port PCI-to-PCI Bridge |
| PI7C8152AMA | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-Port PCI-to-PCI Bridge |
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