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參數(shù)資料
| 型號： | PI7C8150ND |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | 2-Port PCI-to-PCI Bridge |
| 中文描述： | 2端口PCI至PCI橋 |
| 文件頁數(shù)： | 85/106頁 |
| 文件大?。?/td> | 904K |
| 代理商： | PI7C8150ND |
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PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
75
August 22, 2002 – Revision 1.02
14.1.37
UPSTREAM (S TO P) MEMORY LIMIT UPPER 32-BITS
REGISTER – OFFSET 58h
Bit
Function
Upstream
Memory Limit
Address
Type
Description
Defines bits [63:32] of the upstream memory limit
31:0
R/W
Reset to 0
14.1.38
P_SERR_L EVENT DISABLE REGISTER – OFFSET 64h
Bit
0
Function
Reserved
Type
R/O
Description
Reserved. Returns 0 when read. Reset to 0
Controls PI7C8150’s ability to assert P_SERR_L when it is unable to
transfer any read data from the target after 2
attempts.
1
Posted Write
Parity Error
R/W
0: P_SERR_L is asserted if this event occurs and the SERR_L enable
bit in the command register is set.
1: P_SERR_L is not assert if this event occurs.
Reset to 0
Controls PI7C8150’s ability to assert P_SERR_L when it is unable to
transfer delayed write data after 2
attempts.
2
Posted Write
Non-Delivery
R/W
0: P_SERR_L is asserted if this event occurs and the SERR_L enable
bit in the command register is set
1: P_SERR_L is not asserted if this event occurs
Reset to 0
Controls PI7C8150’s ability to assert P_SERR_L when it receives a
target abort when attempting to deliver posted write data.
3
Target Abort
During Posted
Write
R/W
0: P_SERR_L is asserted if this event occurs and the SERR_L enable
bit in the command register is set
1: P_SERR_L is not asserted if this event occurs
Reset to 0
Controls PI7C8150’s ability to assert P_SERR_L when it receives a
master abort when attempting to deliver posted write data.
4
Master Abort On
Posted Write
R/W
0: P_SERR# is asserted if this event occurs and the SERR# enable bit
in the command register is set
1: P_SERR# is not asserted if this event occurs
Reset to 0
Controls PI7C8150’s ability to assert P_SERR# when it is unable to
transfer delayed write data after 2
attempts.
5
Delayed Write
Non-Delivery
R/W
0: P_SERR_L is asserted if this event occurs and the SERR_L enable
bit in the command register is set
1: P_SERR_L is not asserted if this event occurs
Reset to 0
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8150ND-33 | 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 256-Pin BGA 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 256-Pin BGA 制造商:Pericom Semiconductor Corporation 功能描述:PCI BUS CONTROLLER, PBGA256 |
| PI7C8152 | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ENHANCED 2- PORT TO PCI BRIDGE INTEL 21152 COMPORISON |
| PI7C8152A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-Port PCI-to-PCI Bridge |
| PI7C8152A_07 | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-Port PCI-to-PCI Bridge |
| PI7C8152AMA | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-Port PCI-to-PCI Bridge |
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