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參數(shù)資料
| 型號： | PI7C7300ANA |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | 3-PORT PCI-to-PCI BRIDGE |
| 中文描述： | 3端口PCI至PCI橋 |
| 文件頁數(shù)： | 26/109頁 |
| 文件大小： | 779K |
| 代理商： | PI7C7300ANA |
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PI7C7300A
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 26 OF 109
09/25/03 Revision 1.09
Table 4-3 WRITE TRANSACTION DISCONNECT ADDRESS BOUNDARIES
Type of Transaction
Delayed Write
Posted Memory Write
Condition
All
Memory write disconnect control
bit = 0
(1)
Memory write disconnect control
bit = 1
(1)
Cache line size
≠
1, 2, 4, 8, 16
Aligned Address Boundary
Disconnects after one data transfer
4KB aligned address boundary
Posted Memory Write
Disconnects at cache line boundary
Posted Memory Write and
Invalidate
Posted Memory Write and
Invalidate
4KB aligned address boundary
Cache line size = 1, 2, 4, 8, 16
Cache line boundary if posted memory
write data FIFO does not have enough
space for the cache line
Note 1.
Memory write disconnect control bit is bit 1 of the chip control register at offset 40h in the
configuration space.
4.6.5
BUFFERING MULTIPLE WRITE TRANSACTIONS
PI7C7300A continues to accept posted memory write transactions as long as space for at
least one DWORD of data in the posted write data buffer remains. If the posted write
data buffer fills before the initiator terminates the write transaction, PI7C7300A returns a
target disconnect to the initiator.
Delayed write transactions are posted as long as at least one open entry in the delayed
transaction queue exists. Therefore, several posted and delayed write transactions can
exist in data buffers at the same time. See Chapter 6 for information about how multiple
posted and delayed write transactions are ordered.
4.6.6
FAST BACK-TO-BACK WRITE TRANSACTIONS
PI7C7300A can recognize and post fast back-to-back write transactions. When
PI7C7300A cannot accept the second transaction because of buffer space limitations, it
returns a target retry to the initiator. The fast back-to-back enable bit must be set in the
command register for upstream write transactions, and in the bridge control register for
downstream write transactions.
4.7
READ TRANSACTIONS
Delayed read forwarding is used for all read transactions crossing PI7C7300A. Delayed
read transactions are treated as either prefetchable or non-prefetchable. Table 4-4 shows
the read behavior, prefetchable or non-prefetchable, for each type of read operation.
4.7.1
PREFETCHABLE READ TRANSACTIONS
A prefetchable read transaction is a read transaction where PI7C7300A performs
speculative DWORD reads, transferring data from the target before it is requested from
the initiator. This behavior allows a prefetchable read transaction to consist of multiple
data transfers. However, byte enable bits cannot be forwarded for all data phases as is
done for the single data phase of the non-prefetchable read transaction. For prefetchable
read transactions, PI7C7300A forces all byte enable bits to be turned on for all data
phases.
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PDF描述 |
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| PI7C8148B | 2-PORT PCI-to-PCI BRIDGE PLX PC16152 COMPARISON |
| PI7C8150B-33 | PCI Bridge | Asynchronous 2-Port PCI Bridge |
| PI7C8152B | PCI Bridge | Asynchronous 2-Port PCI Bridge |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C7300ANAE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 3 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C7300ANA-E | 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 272-Pin BGA 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 272-Pin BGA |
| PI7C7300DNAE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI PCI -to -PCI Bridge 3 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C7300EVB | 功能描述:界面開發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C8140A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT PCI TO PCI BRIDGE PLX PCI 6140 COMPARISON |
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