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參數(shù)資料
| 型號： | PI7C7300ANA |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | 3-PORT PCI-to-PCI BRIDGE |
| 中文描述： | 3端口PCI至PCI橋 |
| 文件頁數(shù)： | 13/109頁 |
| 文件大小： | 779K |
| 代理商： | PI7C7300ANA |
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PI7C7300A
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 13 OF 109
09/25/03 Revision 1.09
3
SIGNAL DEFINITIONS
3.1
SIGNAL TYPES
Signal Type
PI
PIU
PID
PO
PB
PSTS
Description
PCI input (3.3V, 5V tolerant)
PCI input (3.3V, 5V tolerant) with weak pull-up
PCI input (3.3V, 5V tolerant) with weak pull-down
PCI output (3.3V)
PCI tri-state bidirectional (3.3V, 5V tolerant)
PCI sustained tri-state bi-directional (Active LOW signal which must be driven
inactive for one cycle before being tri-stated to ensure HIGH performance on a
shared signal line)
PCI tri-state output
PCI output which either drives LOW (active state) or tri-state
PTS
POD
3.2
PRIMARY BUS INTERFACE SIGNALS
Name
P_AD[31:0]
Pin #
Y7, W7, Y8, W8,
V8, U8, Y9, W9,
W10, V10, Y11,
V11, U11, Y12,
W12, V12, V16,
W16, Y16, W17,
Y17, U18, W18,
Y18, U19, W19,
Y19, U20, V20,
Y20, T17, R17
V9, U12, U16,
V19
Type
PB
Description
Primary Address/Data.
Multiplexed address and data
bus. Address is indicated by P_FRAME# assertion.
Write data is stable and valid when P_IRDY# is
asserted and read data is stable and valid when
P_TRDY# is asserted. Data is transferred on rising
clock edges when both P_IRDY# and P_TRDY# are
asserted. During bus idle, PI7C7300A drives P_AD to
a valid logic level when P_GNT# is asserted.
P_CBE[3:0]
PB
Primary Command/Byte Enables.
Multiplexed
command field and byte enable field. During address
phase, the initiator drives the transaction type on these
pins. The initiator then drives the byte enables during
data phases. During bus idle, PI7C7300A drives
P_CBE[3:0] to a valid logic level when P_GNT# is
asserted.
Primary Parity.
Parity is even across P_AD[31:0],
P_CBE[3:0], and P_PAR (i.e. an even number of 1’s).
P_PAR is an input and is valid and stable one cycle
after the address phase (indicated by assertion of
P_FRAME#) for address parity. For write data phases,
P_PAR is an input and is valid one clock after
P_IRDY# is asserted. For read data phase, P_PAR is
an output and is valid one clock after P_TRDY# is
asserted. Signal P_PAR is tri-stated one cycle after the
P_AD lines are tri-stated. During bus idle, PI7C7300A
drives P_PAR to a valid logic level when P_GNT# is
asserted.
Primary FRAME (Active LOW).
Driven by the
initiator of a transaction to indicate the beginning and
duration of an access. The de-assertion of P_FRAME#
indicates the final data phase requested by the initiator.
Before being tri-stated, it is driven to a de-asserted
state for one cycle.
P_PAR
U15
PB
P_FRAME#
W13
PSTS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C8140A | 2 PORT PCI TO PCI BRIDGE PLX PCI 6140 COMPARISON |
| PI7C8148B | 2-PORT PCI-to-PCI BRIDGE PLX PC16152 COMPARISON |
| PI7C8150B-33 | PCI Bridge | Asynchronous 2-Port PCI Bridge |
| PI7C8152B | PCI Bridge | Asynchronous 2-Port PCI Bridge |
| PI7C8154 | PCI Bridge | 2-Port PCI-to-PCI Bridge |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C7300ANAE | 功能描述:外圍驅(qū)動器與原件 - PCI 3 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C7300ANA-E | 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 272-Pin BGA 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 272-Pin BGA |
| PI7C7300DNAE | 功能描述:外圍驅(qū)動器與原件 - PCI PCI -to -PCI Bridge 3 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C7300EVB | 功能描述:界面開發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C8140A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT PCI TO PCI BRIDGE PLX PCI 6140 COMPARISON |
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