![](http://datasheet.mmic.net.cn/260000/PI7C7100_datasheet_15942606/PI7C7100_77.png)
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09/18/00 Rev 1.1
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PI7C7100
ADVANCE INFORMATION
13.2.45 Config Register 1 or 2: Master Timeout Counter Register (read/write, bit 31-16; offset 74h)
This register holds the maximum number of PCI clocks that PI7C7100 will wait for initiator to retry the same cycle
before reporting timeout. Default is 8000h.
13.2.46 Config Register 1 or 2: Retry Counter Register (read/write, bit 31-0; offset 78h)
This register holds the maximum number of attempts that PI7C7100 will try before reporting retry timeout.
Default is 0100_0000h.
13.2.47 Config Register 1 or 2: Sampling Timer Register (read/write, bit 31-0; offset 7Ch)
This register set the duration (in PCI clocks) during which PI7C7100 will record the number of successful transactions
for performance evaluation. The recording will start right after this register is programmed and will be cleared after the
timer expires. The maximum period is 128 seconds. Reset to 0000_0000h.
13.2.48 Config Register 1 or 2: Successful I/O Read Count Register (read/write, bit 31-0; offset 80h)
This register stores the successful I/O read count on the secondary interface which will be updated when the sam-
pling timer is active. Reset to 0000_0000h.
13.2.49 Config Register 1 or 2: Successful I/O Write Count Register (read/write, bit 31-0; offset 84h)
This register stores the successful I/O write count on the secondary interface which will be updated when the sam-
pling timer is active. Reset to 0000_0000h.
1
3.2.50 Config Register 1 or 2: Successful Memory Read Count Register (read/write, bit 31-0; offset 88h)
This register stores the successful memory read count on the secondary interface which will be updated when the
sampling timer is active. Reset to 0000_0000h.
13.2.51 Config Register 1 or 2: Successful Memory Write Count Register (read/write, bit 31-0; offset 8Ch)
This register stores the successful memory write count on the secondary interface which will be updated when the
sampling timer is active. Reset to 0000_0000h.
13.2.52 Config Register 1: Primary Successful I/O Read Count Register
(read/write, bit 31-0; offset 90h)
This register stores the successful I/O read count on the primary interface which will be updated when the sampling
timer is active. Reset to 0000_0000h.
13.2.53 Config Register 1: Primary Successful I/O Write Count Register
(read/write, bit 31-0; offset 94h)
This register stores the successful I/O write count on the primary interface which will be updated when the sampling
timer is active. Reset to 0000_0000h.
13.2.54 Config Register 1: Primary Successful Memory Read Count Register
(read/write, bit 31-0; offset 98h)
This register stores the successful memory read count on the primary interface which will be updated when the
sampling timer is active. Reset to 0000_0000h.
13.2.55 Config Register 1: Primary Successful Memory Write Count Register
(read/write, bit 31-0; offset 9Ch)
This register stores the successful memory write count on the primary interface which will be updated when the
sampling timer is active. Reset to 0000_0000h.