- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄368020 > PI7C7100CNA (Pericom Semiconductor Corp.) 3-Port PCI Bridge PDF資料下載
參數(shù)資料
| 型號(hào)： | PI7C7100CNA |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | 3-Port PCI Bridge |
| 中文描述： | 3端口PCI橋 |
| 文件頁(yè)數(shù)： | 40/132頁(yè) |
| 文件大?。?/td> | 2559K |
| 代理商： | PI7C7100CNA |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)當(dāng)前第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)
32
09/18/00 Rev 1.1
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456
6. Transaction Ordering
PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
To maintain data coherency and consistency, PI7C7100 complies with the ordering rules set forth in the PCI Local Bus
Specification, Revision 2.1, for transactions crossing the bridge. This chapter describes the ordering rules that control
transaction forwarding across PI7C7100.
6.1 Transactions Governed by Ordering Rules
Ordering relationships are established for the following classes of transactions crossing PI7C7100:
Posted write transactions, comprised of memory write and memory write and invalidate transactions.
Posted write transactions complete at the source before they complete at the destination; that is, data is written
into intermediate data buffers before it reaches the target.
Delayed write request transactions, comprised of I/O write and configuration write transactions.
Delayed write requests are terminated by target retry on the initiator bus and are queued in the delayed transaction
queue. A delayed write transaction must complete on the target bus before it completes on the initiator bus.
Delayed write completion transactions, comprised of I/O write and configuration write transactions.
Delayed write completion transactions complete on the target bus, and the target response is queued in the
buffers. A delayed write completion transaction proceeds in the direction opposite that of the original delayed write
request; that is, a delayed write completion transaction proceeds from the target bus to the initiator bus.
Delayed read request transactions, comprised of all memory read, I/O read, and configuration read
transactions.
Delayed read requests are terminated by target retry on the initiator bus and are queued in the delayed transaction
queue.
Delayed read completion transactions, comprised of all memory read, I/O read, & configuration read
transactions.
Delayed read completion transactions complete on the target bus, and the read data is queued in the read data
buffers. A delayed read completion transaction proceeds in the direction opposite that of the original delayed read
request; that is, a delayed read completion transaction proceeds from the target bus to the initiator bus.
PI7C7100 does not combine or merge write transactions:
PI7C7100 does not combine separate write transactions into a single write transaction—this optimization is best
implemented in the originating master.
PI7C7100 does not merge bytes on separate masked write transactions to the same DWORD address—this
optimization is also best implemented in the originating master.
PI7C7100 does not collapse sequential write transactions to the same address into a single write transaction—the
PCI Local Bus Specification does not permit this combining of transactions.
6.2 General Ordering Guidelines
Independent transactions on primary and secondary buses have a relationship only when those transactions cross
PI7C7100.
The following general ordering guidelines govern transactions crossing PI7C7100:
The ordering relationship of a transaction with respect to other transactions is determined when the transaction
completes, that is, when a transaction ends with a termination other than target retry.
Requests terminated with target retry can be accepted and completed in any order with respect to other transac-
tions that have been terminated with target retry. If the order of completion of delayed requests is important, the
initiator should not start a second delayed transaction until the first one has been completed. If more than one
delayed transaction is initiated, the initiator should repeat all delayed transaction requests, using some fairness
algorithm. Repeating a delayed transaction cannot be contingent on completion of another delayed transaction.
Otherwise, a deadlock can occur.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C7300 | 3-PORT PCI-to-PCI BRIDGE |
| PI7C7300A | 3-PORT PCI-to-PCI BRIDGE |
| PI7C7300ANA | 3-PORT PCI-to-PCI BRIDGE |
| PI7C8140A | 2 PORT PCI TO PCI BRIDGE PLX PCI 6140 COMPARISON |
| PI7C8148B | 2-PORT PCI-to-PCI BRIDGE PLX PC16152 COMPARISON |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C7300 | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-PORT PCI-to-PCI BRIDGE |
| PI7C7300A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-PORT PCI-to-PCI BRIDGE |
| PI7C7300AEVB-3 | 功能描述:界面開發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C7300ANA | 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 272-Pin BGA 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 272-Pin BGA |
| PI7C7300ANAE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 3 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。