![](http://datasheet.mmic.net.cn/260000/PI7C7100_datasheet_15942606/PI7C7100_29.png)
21
09/18/00 Rev 1.1
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PI7C7100
ADVANCE INFORMATION
PI7C7100 can assert up to 16 unique address lines to be used as IDSEL signals for up to 16 devices on the secondary
bus, for device numbers ranging from 0 through 15. Because of electrical loading constraints of the PCI bus, more than
16 IDSEL signals should not be necessary. However, if device numbers greater than 15 are desired, some external method
of generating IDSEL lines must be used, and no upper address bits are then asserted. The configuration transaction is
still translated and passed from the primary bus to the secondary bus. If no IDSEL pin is asserted to a secondary device,
the transaction ends in a master abort.
PI7C7100 forwards Type 1 to Type 0 configuration read or write transactions as delayed transactions. Type 1 to Type 0
configuration read or write transactions are limited to a single 32-bit data transfer.
4.7.3 Type 1 to Type 1 Forwarding
Type 1 to Type 1 transaction forwarding provides a hierarchical configuration mechanism when two or more levels of PCI-
to-PCI bridges are used.
When PI7C7100 detects a Type 1 configuration transaction intended for a PCI bus downstream from the secondary bus,
PI7C7100 forwards the transaction unchanged to the secondary bus. Ultimately, this transaction is translated to a Type
0 configuration command or to a special cycle transaction by a downstream PCI-to-PCI bridge. Downstream Type 1 to
Type 1 forwarding occurs when the following conditions are met during the address phase:
The lowest two address bits are equal to 01b.
The bus number falls in the range defined by the lower limit (exclusive) in the secondary bus number register and the
upper limit (inclusive) in the subordinate bus number register.
The bus command is a configuration read or write transaction.
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0
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-
Table 4–6. Device Number to IDSEL S1_AD or S2_AD Pin Mapping