參數(shù)資料
型號(hào): PF48F4400P0VTQ0
廠商: INTEL CORP
元件分類: PROM
英文描述: OSC 5V SMT 7X5 CMOS
中文描述: 32M X 16 FLASH 1.8V PROM, 88 ns, PBGA88
封裝: 8 X 11 MM, 1.20 MM HEIGHT, LEAD FREE, SCSP-88
文件頁(yè)數(shù): 84/102頁(yè)
文件大?。?/td> 1609K
代理商: PF48F4400P0VTQ0
1-Gbit P30 Family
April 2005
84
Intel StrataFlash
Embedded Memory (P30)
Order Number: 306666, Revision: 001
Datasheet
5.
The Clear Status command only clears the error bits in the status register if the device is not in the following modes: WSM
running (Pgm Busy, Erase Busy, Pgm Busy In Erase Suspend, OTP Busy, BEFP modes).
BEFP writes are only allowed when the status register bit #0 = 0, or else the data is ignored.
The "current state" is that of the "chip" and not of the "partition"; Each partition "remembers" which output (Array, ID/CFI or
Status) it was last pointed to on the last instruction to the "chip", but the next state of the chip does not depend on where
the partition's output mux is presently pointing to.
Confirm commands (Lock Block, Unlock Block, Lock-Down Block, Configuration Register) perform the operation and then
move to the Ready State.
WA0 refers to the block address latched during the first write cycle of the current operation.
6.
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