參數(shù)資料
型號(hào)： PF48F4400P0VTQ0
廠商： INTEL CORP
元件分類： PROM
英文描述： OSC 5V SMT 7X5 CMOS
中文描述： 32M X 16 FLASH 1.8V PROM, 88 ns, PBGA88
封裝： 8 X 11 MM, 1.20 MM HEIGHT, LEAD FREE, SCSP-88
文件頁(yè)數(shù)： 46/102頁(yè)
文件大?。?/td> 1609K
代理商： PF48F4400P0VTQ0
1-Gbit P30 Family
April 2005
46
Intel StrataFlash
Embedded Memory (P30)
Order Number: 306666, Revision: 001
Datasheet
8.0
Power and Reset Specifications
8.1
Power Up and Down
Power supply sequencing is not required if VCC, VCCQ, and VPP are connected together; If
VCCQ and/or VPP are not connected to the VCC supply, then V
CC
should attain V
CCMIN
before
applying V
CCQ
and V
PP
. Device inputs should not be driven before supply voltage equals V
CCMIN
.
Power supply transitions should only occur when RST# is low. This protects the device from
accidental programming or erasure during power transitions.
8.2
Reset Specifications
Asserting RST# during a system reset is important with automated program/erase devices because
systems typically expect to read from flash memory when coming out of reset. If a CPU reset
occurs without a flash memory reset, proper CPU initialization may not occur. This is because the
flash memory may be providing status information, instead of array data as expected. Connect
RST# to the same active low reset signal used for CPU initialization.
Also, because the device is disabled when RST# is asserted, it ignores its control inputs during
power-up/down. Invalid bus conditions are masked, providing a level of memory protection.
Num Symbol
P1
t
PLPH
Parameter
Min
100
-
-
60
Max
-
25
25
-
Unit
ns
Notes
1,2,3,4
1,3,4,7
1,3,4,7
1,4,5,6
RST# pulse width low
RST# low to device reset during erase
RST# low to device reset during program
V
CC
Power valid to RST# de-assertion (high)
P2
t
PLRH
μs
P3
t
VCCPH
Notes:
1.
2.
3.
4.
5.
6.
These specifications are valid for all device versions (packages and speeds).
The device may reset if t
is < t
PLPH
MIN, but this is not guaranteed.
Not applicable if RST# is tied to Vcc.
Sampled, but not 100% tested.
If RST# is tied to the V
supply, device will not be ready until t
after V
≥
V
.
If RST# is tied to any supply/signal with V
CCQ
voltage levels, the RST# input voltage must not exceed
V
until V
≥
V
.
Reset completes within t
PLPH
if RST# is asserted while no erase or program operation is executing.
7.
相關(guān)PDF資料
PDF描述
PF48F4444PPVTQ0 Intel StrataFlash Embedded Memory
PF48F0P0VTQ0 Intel StrataFlash Embedded Memory
PF48F2P0VTQ0 Intel StrataFlash Embedded Memory
PF48F3P0VTQ0 Intel StrataFlash Embedded Memory
PF48F4P0VTQ0 Intel StrataFlash Embedded Memory
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PF48F4400P0VTQ0A 制造商:Micron Technology Inc 功能描述:Flash Mem Parallel/Serial 1.8V 512M-Bit 32M x 16 88-Pin SCSP Tray 制造商:Micron Technology Inc 功能描述:NUMPF48F4400P0VTQ0A PF48F4400P0VTQ087456
PF48F4400P0Z0C0 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:StrataFlash? Cellular Memory
PF48F4400P0Z0Q0 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:StrataFlash? Cellular Memory
PF48F4400P0Z0W0 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:StrataFlash? Cellular Memory
PF48F4400P0Z3C0 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:StrataFlash?? Cellular Memory
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*