參數(shù)資料
型號(hào)： PF48F4400P0VTQ0
廠商： INTEL CORP
元件分類： PROM
英文描述： OSC 5V SMT 7X5 CMOS
中文描述： 32M X 16 FLASH 1.8V PROM, 88 ns, PBGA88
封裝： 8 X 11 MM, 1.20 MM HEIGHT, LEAD FREE, SCSP-88
文件頁數(shù)： 55/102頁
文件大小： 1609K
代理商： PF48F4400P0VTQ0
1-Gbit P30 Family
Datasheet
Intel StrataFlash
Embedded Memory (P30)
Order Number: 306666, Revision: 001
April 2005
55
10.3.1
Read Mode
The Read Mode (RM) bit selects synchronous burst-mode or asynchronous page-mode operation
for the device. When the RM bit is set, asynchronous page mode is selected (default). When RM is
cleared, synchronous burst mode is selected.
10.3.2
Latency Count
The Latency Count bits, LC[2:0], tell the device how many clock cycles must elapse from the
rising edge of ADV# (or from the first valid clock edge after ADV# is asserted) until the first data
word is to be driven onto DQ[15:0]. The input clock frequency is used to determine this value.
Figure 28
shows the data output latency for the different settings of LC[2:0].
Synchronous burst with a Latency Count setting of Code 4 will result in zero WAIT state; however,
a Latency Count setting of Code 5 will cause 1 WAIT state (Code 6 will cause 2 WAIT states, and
Code 7 will cause 3 WAIT states) after every four words, regardless of whether a 16-word
boundary is crossed. If RCR[9] (Data Hold) bit is set (data hold of two clocks) this WAIT condition
will not occur because enough clocks elapse during each burst cycle to eliminate subsequent WAIT
states.
Refer to
Table 23, “LC and Frequency Support” on page 56
for Latency Code Settings.
3
Burst Wrap (BW)
0 =Wrap; Burst accesses wrap within burst length set by BL[2:0]
1 =No Wrap; Burst accesses do not wrap within burst length (default)
2:0
Burst Length (BL[2:0])
001 =4-word burst
010 =8-word burst
011 =16-word burst
111 =Continuous-word burst (default)
(Other bit settings are reserved)
Note:
Latency Code 2, Data Hold for a 2-clock data cycle (DH = 1)
WAIT must be deasserted with valid data (WD =
0). Latency Code 2, Data Hold for a 2-cock data cycle (DH=1) WAIT deasserted one data cycle before valid
data (WD = 1) combination is not supported.
Table 22.
Read Configuration Register Description (Sheet 2 of 2)
相關(guān)PDF資料
PDF描述
PF48F4444PPVTQ0 Intel StrataFlash Embedded Memory
PF48F0P0VTQ0 Intel StrataFlash Embedded Memory
PF48F2P0VTQ0 Intel StrataFlash Embedded Memory
PF48F3P0VTQ0 Intel StrataFlash Embedded Memory
PF48F4P0VTQ0 Intel StrataFlash Embedded Memory
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PF48F4400P0VTQ0A 制造商:Micron Technology Inc 功能描述:Flash Mem Parallel/Serial 1.8V 512M-Bit 32M x 16 88-Pin SCSP Tray 制造商:Micron Technology Inc 功能描述:NUMPF48F4400P0VTQ0A PF48F4400P0VTQ087456
PF48F4400P0Z0C0 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:StrataFlash? Cellular Memory
PF48F4400P0Z0Q0 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:StrataFlash? Cellular Memory
PF48F4400P0Z0W0 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:StrataFlash? Cellular Memory
PF48F4400P0Z3C0 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:StrataFlash?? Cellular Memory
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*