參數(shù)資料
型號: PF48F4400P0VTQ0
廠商: INTEL CORP
元件分類: PROM
英文描述: OSC 5V SMT 7X5 CMOS
中文描述: 32M X 16 FLASH 1.8V PROM, 88 ns, PBGA88
封裝: 8 X 11 MM, 1.20 MM HEIGHT, LEAD FREE, SCSP-88
文件頁數(shù): 39/102頁
文件大小: 1609K
代理商: PF48F4400P0VTQ0
1-Gbit P30 Family
Datasheet
Intel StrataFlash
Embedded Memory (P30)
Order Number: 306666, Revision: 001
April 2005
39
Note:
WAIT shown deasserted during asynchronous read mode (RCR[10]=0, Wait asserted low).
1.
WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to
assert either during or one data cycle before valid data.
This diagram illustrates the case in which an n-word burst is initiated to the flash memory array and it is
terminated by CE# deassertion after the first word in the burst.
2.
Figure 18.
Asynchronous Page-Mode Read Timing
R108
R9
R7
R17
R15
R10
R4
R8
R3
R106
R101
R105
R1
R2
A[Max:2] [A]
A[1:0]
ADV#
CE# [E]
OE# [G]
WAIT [T]
DATA [D/Q]
Figure 19.
Synchronous Single-Word Array or Non-array Read Timing
R312
R305
R304
R4
R17
R307
R15
R9
R7
R8
R303
R102
R3
R104
R106
R101
R105
R2
R306
R301
CLK [C]
Address [A]
ADV# [V]
CE# [E]
OE# [G]
WAIT [T]
Data [D/Q]
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