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ISAC-SX
PEB 3086
Description of Functional Blocks
Data Sheet
119
2003-01-30
3.7.3.6
Figure 63
shows the MONITOR interrupt structure of the ISAC-SX. The MONITOR Data
Receive interrupt status
MDR
has two enable bits, MONITOR Receive interrupt Enable
(
MRE
) and MR bit Control (
MRC
). The MONITOR channel End of Reception
MER
,
MONITOR channel Data Acknowledged
MDA
and MONITOR channel Data Abort
MAB
interrupt status bits have a common enable bit MONITOR Interrupt Enable
MIE
.
MRE
prevents the occurrence of
MDR
status, including when the first byte of a packet is
received. When
MRE
is active (1) but
MRC
is inactive, the
MDR
interrupt status is
generated only for the first byte of a receive packet. When both
MRE
and
MRC
are
active,
MDR
is always generated and all received MONITOR bytes - marked by a 1-to-0
transition in MX bit - are stored. (Additionally, an active
MRC
enables the control of the
MR handshake bit according to the MONITOR channel protocol.)
MONITOR Interrupt Logic
Figure 63
MONITOR Interrupt Structure
3.7.4
The Command/Indication channel carries real-time status information between the
ISAC-SX and another device connected to the IOM-2 interface.
1. One C/I channel (called C/I0) conveys the commands and indications between the
layer-1 and the layer-2 parts of the ISAC-SX. It can be accessed by an external layer-
2 device e.g. to control the layer-1 activation/deactivation procedures. C/I0 channel
access may be arbitrated via the TIC bus access protocol. In this case the arbitration
is done in IOM-2 channel 2 (see
Figure 46
).
The C/I0 channel is accessed via register CIR0 (in receive direction, layer-1 to layer-2)
and register CIX0 (in transmit direction, layer-2 to layer-1). The C/I0 code is four bits
long. A listing and explanation of the layer-1 C/I codes can be found in
Chapter 3.5.4
.
C/I Channel Handling
ST
CIC
WOV
MOS
ICD
TRAN
Interrupt
ISTA
ICB
MASK
ICB
ST
CIC
WOV
MOS
ICD
TRAN
MRE
MDR
MER
MIE
MOCR
MDA
MAB
MOSR