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參數(shù)資料
| 型號： | PDI1394P25EC |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1-port 400 Mbps physical layer interface |
| 中文描述： | 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PBGA64 |
| 封裝： | 8 X 8 X 1.05 MM, PLASTIC, LFBGA-64 |
| 文件頁數(shù)： | 39/42頁 |
| 文件大?。?/td> | 233K |
| 代理商： | PDI1394P25EC |
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Philips Semiconductors
Preliminary data
PDI1394P23
2-port/1-port 400 Mbps physical layer interface
2001 Sep 06
39
19.0
The PC0–PC2 terminals are programmed to set the default value of the power-class indicated in the pwr field (bits 21–23) of the transmitted
self-ID packet. Descriptions of the various power-classes are given in Table 21. The default power-class value is loaded following a hardware
reset, but is overridden by any value subsequently loaded into the Pwr_Class field in register 4.
POWER-CLASS PROGRAMMING
Table 21. Power Class Descriptions
PC0–PC2
DESCRIPTION
000
Node does not need power and does not repeat power.
001
Node is self powered, and provides a minimum of 15 W to the bus.
010
Node is self powered, and provides a minimum of 30 W to the bus.
011
Node is self powered, and provides a minimum of 45 W to the bus.
100
Node may be powered from the bus and is using up to 3 W.
101
Node is powered from the bus and uses up to 3 W. No additional power is needed to enable the link.
110
Node is powered from the bus and uses up to 3 W. An additional 3 W is needed to enable the link.
111
Node is powered from the bus and uses up to 3 W. An additional 7 W is needed to enable the link.
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| PDI-15SH | 制造商:Power Dynamics Inc 功能描述: |
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