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參數(shù)資料
| 型號： | PDI1394P25EC |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1-port 400 Mbps physical layer interface |
| 中文描述： | 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PBGA64 |
| 封裝： | 8 X 8 X 1.05 MM, PLASTIC, LFBGA-64 |
| 文件頁數(shù)： | 19/42頁 |
| 文件大?。?/td> | 233K |
| 代理商： | PDI1394P25EC |
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Philips Semiconductors
Preliminary data
PDI1394P23
2-port/1-port 400 Mbps physical layer interface
2001 Sep 06
19
Table 8. Page 7 (Vendor-Dependent) Register Field Descriptions
FIELD
SIZE
2
TYPE
Rd/Wr
DESCRIPTION
Link_Speed
Link speed. This field indicates the top speed capability of the attached LLC. Encoding is as follows:
Code
Speed
00
S100
01
S200
10
S400
11
illegal
This field is replicated in the “sp” field of the self-ID packet to indicate the speed capability of the node
(PHY and LLC in combination). However, this field does not affect the PHY speed capability indicated to
peer PHYs during self-ID; the PDI1394P23 PHY identifies itself as S400 capable to its peers regardless
of the value in this field. This field is set to 10b (S400) by hardware reset and is unaffected by bus-reset.
An 11b can be written into this field, however, a 10b will be sent in the self-ID packet.
Bridge_Aware
2
Rd/Wr
Bridge_Aware. This field reports Bridge_Aware capability to all nodes via the self-ID packet. Encoding
is as follows:
Code
Meaning
00
Non-bridge device
01
Reserved (BRAN Bridge)
10
Bridge compliant with 1394.1 (unchanged state)
11
Bridge compliant with 1394.1 (changed state)
This field is replicated in bits 18 and 19 of the self-ID packet. The value of this field does not affect PHY
operation. It is a reporting mechanism. The default value for this field is set by the BRIDGE pin. The
BRIDGE pin is sampled during a hardware reset (RESET low). When the BRIDGE pin is low, this field
is set to “00” indicating a “non-bridge device.” When the BRIDGE pin is high, this field is set to “11”
indicating a “1394.1 bridge compliant” device. Writing to this field overrides the default setting by the
BRIDGE pin.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PDI1394P23BD | 2-port/1-port 400 Mbps physical layer interface |
| PDI1394L41BE | 8358 PBGA ENCRP NO-PB |
| PDI1394P21BE | 3-port physical layer interface |
| PDI1394P22BD | 3-port physical layer interface |
| PDI1394L11BA | 1394 AV link layer controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PDI-15R | 制造商:Power Dynamics Inc 功能描述: |
| PDI-15RH-5 | 制造商:Power Dynamics Inc 功能描述: |
| PDI-15RH-5-R-G30 | 制造商:Power Dynamics Inc 功能描述:PDI Series 15 Position Right Angle Socket High Density D-Sub |
| PDI-15S | 制造商:POWER DYNAMICS 功能描述: 制造商:Power Dynamics Inc 功能描述: |
| PDI-15SH | 制造商:Power Dynamics Inc 功能描述: |
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