參數(shù)資料
型號(hào)： PDI1394P25EC
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 1-port 400 Mbps physical layer interface
中文描述： 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PBGA64
封裝： 8 X 8 X 1.05 MM, PLASTIC, LFBGA-64
文件頁(yè)數(shù)： 33/42頁(yè)
文件大?。?/td> 233K
代理商： PDI1394P25EC
Philips Semiconductors
Preliminary data
PDI1394P23
2-port/1-port 400 Mbps physical layer interface
2001 Sep 06
33
Table 20. LPS Timing Parameters
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
T
LPSL
T
LPSH
LPS low time (when pulsed) (see Note 1)
0.09
2.60
μ
S
LPS high time (when pulsed) (see Note 1)
0.021
2.60
μ
S
LPS duty cycle (when pulsed) (see Note 2)
20
55
%
T
LPS_RESET
T
LPS_DISABLE
T
RESTORE
T
CLK_ACTIVATE
Time for PHY to recognize LPS deasserted and reset the interface
2.60
2.68
μ
S
Time for PHY to recognize LPS deasserted and disable the interface
26.03
26.11
23
3
μ
S
Time to permit optional isolation circuits to restore during an interface reset
15
μ
S
Time for SYSCLK to be activated from reassertion of LPS
—
60
nS
NOTES:
1. The specified T
LPSL
and T
LPSH
times are worst–case values appropriate for operation with the PDI1394P23. These values are broader than
those specified for the same parameters in the P1394a Supplement (i.e., an implementation of LPS that meets the requirements of P1394a
will operate correctly with the PDI1394P23).
2. A pulsed LPS signal must have a duty cycle (ratio of T
to cycle period) in the specified range to ensure proper operation when using an
isolation barrier on the LPS signal (e.g., as shown in Figure 8)
3. The maximum value for T
does not apply when the PHY–LLC interface is disabled, in which case an indefinite time may elapse
before LPS is reasserted. Otherwise, in order to reset but not disable the interface it is necessary that the LLC ensure that LPS is
deasserted for less than T
LPS_DISABLE
.
The LLC requests that the interface be reset by deasserting the LPS
signal and terminating all bus and request activity. When the PHY
observes that LPS has been deasserted for T
LPS_RESET
, it resets
the interface. When the interface is in the reset state, the PHY sets
its CTL and D outputs in the logic 0 state and ignores any activity on
the LREQ signal. The timing for interface reset is shown in Figure 20
and Figure 21.
T
LPS_RESET
T
RESTORE
ISO
SYSCLK
CTL0, CTL1
D0 – D7
LREQ
LPS
(low)
(a)
(c)
(d)
(b)
T
LPSL
T
LPSH
SV01810
Figure 20.
Interface Reset, ISO Low
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