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參數(shù)資料
| 型號： | PDI1394P25EC |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1-port 400 Mbps physical layer interface |
| 中文描述： | 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PBGA64 |
| 封裝： | 8 X 8 X 1.05 MM, PLASTIC, LFBGA-64 |
| 文件頁數(shù)： | 2/42頁 |
| 文件大小： | 233K |
| 代理商： | PDI1394P25EC |
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Philips Semiconductors
Preliminary data
PDI1394P23
2-port/1-port 400 Mbps physical layer interface
2
2001 Sep 06
1.0
Fully supports provisions of IEEE 1394–1995 Standard for high
performance serial bus and the P1394a–2000 Standard.
1
Fully interoperable with Firewire
and i.LINK
implementations of
the IEEE 1394 Standard.
2
Full P1394a support includes:
–
Connection debounce
–
Arbitrated short reset
–
Multispeed concatenation
–
Arbitration acceleration
–
Fly-by concatenation
–
Port disable/suspend/resume
Provides two 1394a fully-compliant cable ports at
100/200/400 Mbps.
Fully compliant with Open HCI requirements
Interface to link-layer controller supports both low-cost bus-holder
isolation and optional Annex J electrical isolation
Supports extended bias-handshake time for enhanced
interoperability with camcorders
Data interface to link-layer controller through 2/4/8 parallel lines at
49.152 MHz
Register bits give software control of contender bit, power class
bits, link active bit, and 1394a features
Cable ports monitor line conditions for active connection to remote
node.
Separate cable bias (TPBIAS) for each port
Logic performs system initialization and arbitration functions
Encode and decode functions included for data-strobe bit level
encoding
Incoming data resynchronized to local clock
Single 3.3 volt supply operation
Minimum V
DD
of 2.7 V for end-of-wire power-consuming devices
FEATURES
Interoperable with link-layer controllers using 3.3 V and 5 V
supplies
Interoperable with other Physical Layers (PHYs) using 3.3 V and
5 V supplies
Node power class information signaling for system power
management
Cable power presence monitoring
Power down features to conserve energy in battery-powered
applications include:
–
Automatic device power down during suspend
–
Device power down terminal
–
Link interface disable via LPS
–
Inactive ports powered-down
While unpowered and connected to the bus, will not drive TPBIAS
on a connected port, even if receiving incoming bias voltage on
that port
Can be used as a one port PHY without the use of any extra
external components
Low-cost 24.576 MHz crystal provides transmit, receive data at
100/200/400 Mbps, and link-layer controller clock at 49.152 MHz
Does not require external filter capacitors for PLL
LQFP package is function and pin compatible with the Texas
Instruments TSB41LV02AE
and TSB41AB2E
400 Mbps
PHYs.
2.0
The PDI1394P23 provides the digital and analog transceiver functions
needed to implement a two/one port node in a cable-based IEEE
1394–1995 and/or 1394a–2000 network. Each cable port incorporates
two differential line transceivers. The transceivers include circuitry to
monitor the line conditions as needed for determining connection
status, for initialization and arbitration, and for packet reception and
transmission. The PDI1394P23 is designed to interface with a Link
Layer Controller (LLC), such as the PDI1394L40, or PDI1394L41.
DESCRIPTION
3.0
ORDERING INFORMATION
PACKAGE
TEMPERATURE RANGE
ORDER CODE
PKG. DWG. #
64-pin plastic LQFP
0 to +70
°
C
PDI1394P23BD
SOT314-2
64-ball plastic LFBGA
0 to +70
°
C
PDI1394P23EC
SOT534-1
1.
2.
Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thompson, Limited.
Firewire is a trademark of Apple Computer Inc. i.LINK is a trademark of Sony.
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