
-
164
-
2-6.
RENV4
register
Bit
7
(C1RM),
bit
15
(C2RM)
and
bit
23
(IDXM)
have
been
added.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
C2RM
C2D1 C2D0 C2S2 C2S1
C2C1
C2S0
C2C0 C1RM C1D1 C1D0 C1S2 C1S1 C1S0 C1C1 C1C0
Bit
7
15
23
Bit
name
C1RM 1:
Sets
COUNTER1
for
ring
counter
operation
using
Comparator
1.
C2RM 1:
Sets
COUNTER2
for
ring
counter
operation
using
Comparator
2.
IDXM
0:
Output
an
IDX
signal
while
COUNTER4
=
RCMP2.
1:
When
COUNTER4
becomes
"0"
by
counting
down,
the
PCL
will
output
an
IDX
signal
for
two
CLK
cycles.
(This
is
only
valid
when
C4S0
to
C4S3
are
set
to
1000,
1001
or
1010.)
Detail
2-7.
RENV5
register
Bits
24
(CU1L)
to
bit
27
(CU4L)
have
been
added.
Bit
24
25
26
27
Bit
name
CU1L
CU2L
CU3L
CU4L
Details
1:
The
PCL
clears
COUNTER1
at
the
same
time
it
latches
COUNTER1.
1:
The
PCL
clears
COUNTER2
at
the
same
time
it
latches
COUNTER2.
1:
The
PCL
clears
COUNTER3
at
the
same
time
it
latches
COUNTER3.
1:
The
PCL
clears
COUNTER4
at
the
same
time
it
latches
COUNTER4.
2-8.
RENV6
register
Bit
15
(PSTP),
bits
16
to
26
(BD0
to
10),
and
bits
27
to
31
(REG0
to
4)
have
been
added.
Bit
15
Bit
name
PSTP
Detail
1:
Even
when
a
stop
command
is
written,
the
pulses
already
input
on
PA/PB
will
be
fed.
PD0
to
10 Set
the
PA/PB
division
rate
[Divide
by
(set
value
/
2048)]
27
to
31 PMG0
to
4 Set
the
PA/PB
multiplication
rate
[enter
(multiplication
value
-
1)]
16
to
26
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PSTP
0
ADJ1 ADJ0 BR11
BR9
BR10
BR8
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
PMG4 PMG3 PMG2 PMG1 PMG0 PD10 PD9
PD8
BR7
BR6
BR5
BR4
BR3
BR2
BR1
BR0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
C4D1 C2D0 C4S3 C4S2 C4S1 C4S0 C4C1 C4C0 IDXM C3D1 C3D0 C3S2 C3S1 C3S0 C3C1 C3C0